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Loongson 3A3000 User Manual Download Page 101

4/29/2020

Loongson 3A3000 / 3B3000 Processor User Manual

101

121

10: 32 cycles

11: 128 cycles

15: 8

level

Read and write 8'h01

Equipment in the first level

23:16

 ude_dev

Read-write 0

Mandatory priority device

The PCI device corresponding to the 1 bit can be obtained after the bus

To occupy the bus with continuous requests

31:13

Keep

Read only 0

CR6C: PXA   b_Status

7: 0

b   

耀

 ken_maste 

Read only 0

Damaged master device (cleared when changing the disable policy)

10: 8

Last_maste

Read only 0

Last master device using the bus

31:11

Keep

Read only 0

CR80: Ch pc Yao nf g (see section 2.6)

CR90: Ch p Sample (see section 2.6)

CRA0: Ch p Sample (see section 2.6)

CRB0: PLL c Yao nf g (see section 2.6)

CRC0: PLL c Yao nf g (see section 2.6)

CRD0: C Yao Yi ec Yao nf g (see section 2.6)

Page 126

12 Chip Configuration Register List

Name

ADDR

R / W

Description (NULL means no effect)

default value

CPU_WIN0_BASE

0x3ff00000

RW

Base address of CPU window 0

0x0

CPU_WIN1_BASE

0x3ff00008

RW

Base address of CPU window 1

0x1000_0000

CPU_WIN2_BASE

0x3ff00010

RW

Base address of CPU window 2

0x1000_8000_0000

CPU_WIN3_BASE

0x3ff00018

RW

Base address of CPU window 3

0x0

CPU_WIN4_BASE

0x3ff00020

RW

Base address of CPU window 4

0x0

CPU_WIN5_BASE

0x3ff00028

RW

Base address of CPU window 5

0x0

Summary of Contents for 3A3000

Page 1: ...r Manual 1 Page 1 Loongson 3A3000 3B3000 processor User Manual volume One Multi core processor architecture register description and system software programming guide V1 3 2017 Nian 4 Yue Loongson Zho...

Page 2: ...ation Limited Address Building 2 Longxin Industrial Park Zhongguancun Environmental Protection Technology Demonstration Park Haidian District Beijing Building No 2 Loongson Industrial Park Zhongguancu...

Page 3: ...er update content 1 2016 06 14 V1 0 initial version 2 2016 09 14 V1 1 Updated some PLL configuration register descriptions updated software and hardware changes descriptions 3 2016 11 25 V1 2 Add regi...

Page 4: ...uration and Sampling Register 25 3 GS464e processor core 30 4 Shared Cache SCache 32 5 Matrix processing accelerator 34 6 Interruption and communication between processor cores 37 7 I O interrupt 40 8...

Page 5: ...64 10 5 1 Bridge Control 66 10 5 2 Capability Registers 66 10 5 3 User defined register 69 10 5 4 Receive diagnostic register 71 10 5 5 Interrupt routing mode selection register 71 10 5 6 Receive buff...

Page 6: ...PCI Controller 101 11 2 LPC Controller 106 11 3 UART Controller 107 11 3 1 Data Register DAT 108 11 3 2 Interrupt Enable Register IER 108 11 3 3 Interrupt Identification Register IIR 108 11 3 4 FIFO...

Page 7: ...p structure 13 Figure 3 1 GS464e structure diagram 31 Figure 7 1 Loongson 3A3000 3B3000 processor interrupt routing diagram 40 Figure 9 1 DDR2 SDRAM read operation protocol 47 Figure 9 2 DDR2 SDRAM wr...

Page 8: ...ode and processor core software frequency multiplication setting register physical address 0x1fe001b0 27 Table 2 14 Chip memory and HT clock software frequency multiplier setting register physical add...

Page 9: ...Revision ID Link Freq Link Error Link Freq Cap Registers 68 Table 10 12 Definition of Feature Capability Register 69 Table 10 13 MISC register definition 69 Table 10 14 Receive Diagnostic Register 71...

Page 10: ...Access 83 Table 10 49 HT Bus POST Address Window 1 Base Address Internal Access 83 Table 10 50 HT Bus Prefetchable Address Window 0 Enable Internal Access 83 Table 10 51 HT Bus Prefetchable Address W...

Page 11: ...Table 10 78 Training 3 Count Register 95 Table 10 79 Software Frequency Configuration Register 95 Table 10 80 PHY Configuration Register 96 Table 10 81 Link Initialization Debug Register 97 Table 10 8...

Page 12: ...ti core interconnect architecture design integrating multiple high performance on a single chip The processor core and a large number of level 2 caches and the interconnection of multiple chips throug...

Page 13: ...connected to the four directions of east south west and north through four pairs of Master Slave Other nodes or IO nodes EM ES SM SS WM WS NM NS in the figure The X2 crossbar is connected to four shar...

Page 14: ...n 3A3000 3B3000 chip is based on two level interconnection The structure is shown in Figures 1 3 below Figure 1 3 Loongson 3A3000 3B3000 chip structure The first level interconnection uses a 6x6 cross...

Page 15: ...3000 which is a symmetric multiprocessor system SMP Multi chip interconnect mode The system contains 2 or 4 Loongson 3A3000 3B3000 through Loongson The HT ports of 3A3000 3B3000 are interconnected whi...

Page 16: ...controller clock is divided by 4 of the PHY clock 2 b10 means the HT controller clock is divided by 2 of the PHY clock 2 b11 indicates that the HT controller clock is SYSCLOCK Note When CLKSEL 13 10 4...

Page 17: ...of the address the entire address sp It is evenly distributed to 16 nodes that is each node is allocated 44 bit address space Loongson 3A3000 3B3000 processor can directly use 4 chips to connect direc...

Page 18: ...hown in the following table In default In this case it is distributed by means of 7 6 status hash that is two bits of address 7 6 determine the corresponding shared cache number The register address i...

Page 19: ...e table below Table 2 6 Register Table of Address Window of Primary Crossbar address register address register 0x3ff0_2000 CORE0_WIN0_BASE 0x3ff0_2100 CORE1_WIN0_BASE 0x3ff0_2008 CORE0_WIN1_BASE 0x3ff...

Page 20: ...x3ff0_2288 CORE2_WIN1_MMAP 0x3ff0_2388 CORE3_WIN1_MMAP 0x3ff0_2290 CORE2_WIN2_MMAP 0x3ff0_2390 CORE3_WIN2_MMAP 0x3ff0_2298 CORE2_WIN3_MMAP 0x3ff0_2398 CORE3_WIN3_MMAP 0x3ff0_22a0 CORE2_WIN4_MMAP 0x3ff...

Page 21: ...following table 63 48 47 10 7 4 3 0 Interleaved selection bit Address after conversion Window enable Slave number Among them the device corresponding to the slave device number is shown in the follow...

Page 22: ...68 CPU_WIN5_MASK Mask of CPU window 5 0x0 3ff0 0070 CPU_WIN6_MASK CPU window 6 mask 0x0 3ff0 0078 CPU_WIN7_MASK CPU window 7 mask 0x0 3ff0 0080 CPU_WIN0_MMAP CPU window 0 new base address 0xf0 3ff0 00...

Page 23: ...ress range of 0x00000000 0x0fffffff of DDR2 0x10000000 of CPU 0x1fffffff interval 256M is mapped to PCI 0x10000000 0x1fffffff interval PCIDMA 0x80000000 The address range 256M of 0x8fffffff is mapped...

Page 24: ...nsor 0 overflow over 125 89 Thsens1_overflow R Temperature sensor 1 overflow over 125 111 96 Thsens0_out R Temperature sensor 0 Celsius Knot point temperature degree Thens0_out 731 0x4000 273 Temperat...

Page 25: ...ass L1 PLL 15 4 RW 0x0 16 LOCKED_L1 R 0x0 Whether L1 PLL is locked 17 LOCKED_L2 R 0x0 Whether L2 PLL is locked 18 17 R 0x0 19 PD_L1 RW 0x0 Turn off L1 PLL 20 PD_L2 RW 0x0 Turn off L2 PLL twenty one tw...

Page 26: ..._OUT RW 0x0 MEM PLL input parameters 30 NODE_CLOCK_SEL RW 0x0 0 Use MEM_PLL as the MEM clock 1 Use NODE_CLOCK as the crossover input 32 SEL_HT0_PLL RW 0x0 HT0 non software bypass PLL 33 SOFT_SET_HT0_P...

Page 27: ...p multi core systems for server and high performance applications use Multiple GS464 cores in Loongson 3A3000 3B3000 and shared cache modules are formed via AXI interconnection network It is a multi c...

Page 28: ...ogies Support Cache consistency protocol can be used for on chip multi core processor Instruction Cache implements parity check and Data Cache implements ECC check Support the standard EJTAG debugging...

Page 29: ...nsumption Cache TAG The directory and data can be accessed separately The shared Cache status bit and w bit are stored with the TAG and the TAG is stored in the TAG RAM In the directory is stored in D...

Page 30: ...address of No 1 lock window Sl Yaock1_mask 0x3ff00248 47 0 Lock window mask number 1 Sl Yaock2_val d 0x3ff00210 63 63 Lock window 2 valid bits Sl Yaock2_add 0x3ff00210 47 0 Lock address of No 2 lock w...

Page 31: ...to the SCache is realized The source matrix involved in transposing or moving may be a small matrix located in a large matrix Therefore the matrix address can be If it is not completely continuous the...

Page 32: ...ontrol bit When a cache is 4 hf it must be set to 4 hc It doesn t make sense when a cache is other value 11 8 A Cache read command internal control bit When it is 4 hf the cache path is used and when...

Page 33: ...to transfer parameters at startup according to 64 or 32 bit Uncache access Ma lB Yao x01 RW Cache register used to transfer parameters at startup according to 64 or 32 bit Uncache access Ma lB Yao x02...

Page 34: ...x0 0x3ff01220 R IPI_Ma lB Yao x0 register of processor core 2 C Yao Ya e2_ Ma lB Yao x10x3ff01228 RW IPI_Ma lB Yao x1 register of processor core 2 C Yao Ya e2_ Ma lB Yao x20x3ff01230 W IPI_Ma lB Yao x...

Page 35: ...nd the address of processor 0 of node 1 is 0x10003ff01000 and so on Page 44 Godson 3A3000 3B3000 Processor User Manual Volume 1 7 I O interrupt Loongson 3A3000 3B3000 chip supports up to 32 interrupt...

Page 36: ...User Manual Volume 1 condition The interrupt signal in the form of a pulse such as PCI_SERR is selected by the Intedge configuration register Writing 1 means that the pulse triggers Send write 0 mean...

Page 37: ...routing to INT2 of processor 3 Page 46 Godson 3A3000 3B3000 Processor User Manual Volume 1 Table 7 3 Interrupt Routing Register Description Bit field Explanation 3 0 Routed processor core vector numbe...

Page 38: ...es Through the setting of the control register it is possible to achieve interruptions above the preset temperature interruptions below the preset temperature and high temperature Automatic frequency...

Page 39: ...9 32 Lo_gate2 Low temperature threshold 2 below this temperature will generate an interrupt 40 40 Lo_en2 Low temperature interrupt enable 2 43 42 Lo_Sel2 Select the temperature sensor input source for...

Page 40: ...dson 3A3000 3B3000 Processor User Manual Volume 1 9 DDR2 3 SDRAM controller configuration The design of the integrated memory controller inside Loongson No 3 processor complies with the industry stand...

Page 41: ...AS_n and WE_n are composed of three signals For read operations RAS_n 1 CAS_n 0 and WE_n 1 Page 51 Godson 3A3000 3B3000 Processor User Manual Volume 1 Figure 9 1 DDR2 SDRAM read operation protocol In...

Page 42: ...Enzi_end_3 Enzi_begin_3 Wrclk_sel_3 Wrdq_clkdelay_3 Odt_oe_end_3 Odt_oe_begin_3 Odt_stop_edge_3 Odt_start_edge_3 0x098 Enzi_stop_3 Enzi_start_3 Dll_oe_shorten_3Dll_rddqs_n_3 Dll_rddqs_p_3 Dll_wrdqs_3...

Page 43: ..._3 Mr_0_cs_3 0x1C0 tRESET tCKE tXPR tMOD tZQCL tZQ_CMD tWLDQSEN tRDDATA 0x1C8 tFAW tRRD tRCD tRP tREF tRFC tZQCS tZQperiod 0x1D0 tODTL tXSRD tPHY_RDLAT tPHY_WRLAT tRAS_max tRAS_min 0x1D8 tXPDLL tXP tW...

Page 44: ...rogramming Guide 9 5 1 Initial operation The initialization operation is started when the software writes 1 to the register Init_start 0x018 Set Init_start Before the signal all other registers must b...

Page 45: ...ow Page 56 Godson 3A3000 3B3000 Processor User Manual Volume 1 2 Reverse mode reset_ctrl 1 0 2 b10 In this mode the reset signal pin is in memory In actual control the effective level is opposite to t...

Page 46: ...udes Write Leveling Read Leveling and Gate Leveling In this controller Only Write Leveling and Gate Leveling are implemented Read Leveling is not implemented the software needs to pass judgment The co...

Page 47: ...ite Leveling mode 9 5 3 2 Gate Leveling Gate Leveling is used to configure the timing of enabling the sampling and reading DQS window in the controller Refer to the following steps for software progra...

Page 48: ...he correct values 2 Set Command_mode 0x190 to 1 to make the controller enter the command sending mode 3 Sampling Status_cmd 0x190 if it is 1 it means the controller has entered command sending mode Go...

Page 49: ...ere is an error The specific operations are as follows 6 Sampling register Lpbk_error 0x270 if this value is 1 it means there is an error at this time you can pass Observe the first error through Lpbk...

Page 50: ...tion 10 7 The HyperTransport controller supports up to 16 bit bidirectional width and 2 0GHz operating frequency At the beginning of the system automatically After initializing the connection the user...

Page 51: ...trolled by the opposite device HT0_Lo_Rstn Bus Rstn HyperTransport bus Rstn signal When HT0_Lo_Mode is 1 it is controlled by HT0_Lo When HT0_Lo_Mode is 0 it is controlled by the opposite device HT0_Lo...

Page 52: ...y 200MHz and the smallest width 8bit and try to initiate a bus initialization handshake initialization Whether it is in the completed state can be read from the register Init Complete see Section 10 5...

Page 53: ...erent Read response extension 111001 NPC RdCoherent Read command extension 111011 NPC RdAddr Read address extension 111111 Sync Error Will only forward 10 3 HyperTransport interrupt support The HyperT...

Page 54: ...F_FFFF 30 Mbytes Keep 0xFD_FB00_0000 0xFD_FBFF_FFFF 16 Mbytes HT controller configuration space 0xFD_FC00_0000 0xFD_FDFF_FFFF 32 Mbytes I O space 0xFD_FE00_0000 0xFD_FFFF_FFFF 32 Mbytes HT bus configu...

Page 55: ...number of configuration files that can be seen by the software for controlling the various working modes of Memory First the access and storage of configuration registers used to control various beha...

Page 56: ...nal access 0x16C HT bus Uncache address window 2 base address external access 0x170 HT bus Uncache address window 3 enable external access 0x174 HT bus Uncache address window 3 base address external a...

Page 57: ...OSTMODE drop down 1 25 Reserved 1 0x0 Keep twenty four Host Hide 1 0x0 Whether R W prohibits register access from HT bus twenty three Reserved 1 0x0 Keep 22 18 Unit ID 5 0x0 R W In HOST mode can be us...

Page 58: ...wer 8 bits of R W 7 Trans off 1 0x0 R W HT PHY shutdown control When in 16 bit bus operating mode 1 Turn off high low 8 bit HT PHY 0 enable the low 8 bit HT PHY The upper 8 bit HT PHY is controlled by...

Page 59: ...STOP 1 0x1 R Support LDTSTOP 0 Isochronous Mode 1 0x0 R not support 10 5 3 Custom register Offset 0x50 Reset value 0x00904321 name MISC Table 10 13 MISC register definition Bit field Bit field name Bi...

Page 60: ...4 R W HT bus Nop flow control packet priority 11 8 Priority NPC 4 0x3 R W Non Post channel read and write priority 7 4 Priority RC 4 0x2 R W Response channel reading and writing priority 3 0 Priority...

Page 61: ...rx_buffer_r_cmd 4 0x0 R W receive buffer read command initialization information 7 4 rx_buffer_npc_cmd 4 0x0 R W receive buffer npc command buffer initialization information 3 0 rx_buffer_pc_cmd 4 0x0...

Page 62: ...definition Bit field Bit field name Bit width reset value Visit description 31 ht_rx_image1_en 1 0x0 R W HT bus receives address window 1 enable signal 30 ht_rx_image1_ trans_en 1 0x0 R W HT bus rece...

Page 63: ...Table 10 23 HT Bus Receive Address Window 3 Enable External Access Register Definition Bit field Bit field name Bit width reset value Visit description 31 ht_rx_image3_en 1 0x0 R W HT bus receives ad...

Page 64: ...register 0x50 the order of mapping is INTD INTC INTB INTA 1 b0 INIT NMI SMI At this time the corresponding value of the interrupt vector is Interrupt Index internal The amount 2 0 LS3A1000E and above...

Page 65: ...ding to interrupt line 4 Offset 0x88 Reset value 0x00000000 Page 81 Godson 3A3000 3B3000 Processor User Manual Volume 1 name HT Bus Interrupt Vector Register 95 64 Table 10 29 HT Bus Interrupt Vector...

Page 66: ...line 3 HT HI Corresponding to interrupt line 7 10 5 9 Interrupt enable register A total of 256 interrupt enable registers correspond to the interrupt vector registers Set to 1 to enable the correspon...

Page 67: ...rupt line 4 Offset 0xa4 Reset value 0x00000000 name HT bus interrupt enable register 63 32 Table 10 35 Definition of HT Bus Interrupt Enable Register 2 Bit field Bit field name Bit width reset value V...

Page 68: ...rrupt enable register 223 192 Table 10 40 HT bus interrupt enable register definition 7 Bit field Bit field name Bit width reset value Visit description 31 0 Interrupt_mask 223 192 32 0x0 R W HT bus i...

Page 69: ...Bit field Bit field name Bit width reset value Visit description 31 0 IntrInfo 63 32 32 0x0 R Keep 10 5 11 POST address window configuration register For the address window hit formula see section 10...

Page 70: ...address 39 24 Offset 0xdc Reset value 0x00000000 name HT bus POST address window 1 base address internal access Table 10 49 HT bus POST address window 1 base address internal access Bit field Bit fiel...

Page 71: ...ternal access Table 10 52 HT Bus Prefetchable Address Window 1 Enable Internal Access Bit field Bit field name Bit width reset value Visit description 31 ht_prefetch1_en 1 0x0 R W HT bus can prefetch...

Page 72: ...53 24 Offset 0xf4 Reset value 0x00000000 name HT bus Uncache address window 0 base address internal access Table 10 55 HT Bus Uncache Address Window 0 Base Address Internal Access Bit field Bit field...

Page 73: ...et value Visit description 31 16 ht_uncache1_ base 39 24 16 0x0 R W HT bus uncache address window 2 address base address 39 24 Page 91 Godson 3A3000 3B3000 Processor User Manual Volume 1 Bit field Bit...

Page 74: ...ddress window 0 mapping enable signal 29 0 ht_rx_image2_ trans 53 24 16 0x0 R W HT bus P2P address window 0 translated address 53 24 Offset 0x15c Reset value 0x00000000 name HT bus P2P address window...

Page 75: ...Number of B channel command buffers at the sending end 2316 R_CMD_txbuffer 8 0x0 R Number of R channel command buffers at the sending end 15 8 NPC_CMD_txbuffer 8 0x0 R Number of NPC channel command bu...

Page 76: ...crease and decrease the number of B channel command cache When tx_neg is 0 increase B_CMD_txadj When tx_neg is 1 reduce B_CMD_txadj 1 11 8 R_CMD_txadj 4 0x0 R W sender R channel command cache increase...

Page 77: ...rror Retry Control Register Table 10 71 E Reach Ret Rey Control Register Bit field Bit field name Bit width reset value Visit description 31 10 Reserved twenty two 0x0 R Keep 9 Retry Count Rollover 1...

Page 78: ...in consecutive DWS 1 b0 Enable Cmd Throttling 1 b1 Disable Cmd Throttling 13 10 Reserved 4 0x0 R Keep 8 7 Receiver LS select 2 0x0 The R W receiver is at Disconnected or Inactive Link status 2 b00 LS...

Page 79: ...aining 1 count register Used in Training 1 counting threshold in HyerTransport 3 0 mode the counter clock frequency is HyperTransport3 0 link bus clock frequency is 1 4 Offset 0x13C Reset value 0x0004...

Page 80: ...tically reset the PLL and configure new clock parameters The calculation formula of the clock frequency is HyperTransport 1 0 PHY_LINK_CLK 50MHz div_loop div_refc phy_div HT_CORE_CLK 100MHz div_loop d...

Page 81: ...e termination impedance 30 Tx_ckpll_term 1 0x0 R W PLL to TX terminal on chip transmission line termination impedance 29 Rx_clk_in_sel_ 1 0x0 R W Clock PAD Clock selection for data PAD HT1 Automatical...

Page 82: ...value 0x00000000 Page 102 Godson 3A3000 3B3000 Processor User Manual Volume 1 name LDT debug register Table 10 82 LDT debug registers Bit field Bit field name Bit width reset value Visit description 3...

Page 83: ...When routing X followed by Y taking four chips as an example ID The numbers are 00 01 10 and 11 respectively If you send a request from 11 to 00 it is a route from 11 to 00 first go in the X directio...

Page 84: ...de of CPU0 and CPU1 You can use the 16 bit HT bus interconnection to set and connect the high and low bus correctly And this interconnect structure can also be used 8 Bit HT bus protocol for mutual ac...

Page 85: ...n Spec fc Reg ste ISR40 40 Implementat Yaon Spec fc Reg ste ISR44 44 Implementat Yao n Spec fc Reg ste ISR48 48 Implementat Yao n Spec fc Reg ste ISR4C 4C Implementat Yaon Spec fc Reg ste ISR50 50 Im...

Page 86: ...lume 1 12 5 delay visit 13 6 delay visit 14 7 delay visit 15 8 delay visit 15 4 ta _p ef_b Yao unda y Read and write 000h Prefetchable boundary configuration in units of 16 bytes FFF 64KB to 16byte FF...

Page 87: ...ved 29 28 ta _spl t_p ty Read and write 0 ta get spl t return priority 0 highest 3 lowest 27 26 mas_ eq_p ty Read and write 0 maste 0 highest 3 lowest 25 P ty_en Read and write 0 Arbitration algorith...

Page 88: ...is rotated once and the device with the highest priority in the second level can get the bus The arbiter is designed to be switched at any time as long as conditions permit For some PCI devices that d...

Page 89: ...n Type of access The LPC Memory address space is the address space accessed by the system with Memory Firmware Memory LPC controller Which type of memory access is issued is determined by the configur...

Page 90: ...l address of the UART1 register is 0x1FE001E8 Page 112 Godson 3A3000 3B3000 Processor User Manual Volume 1 11 3 1 Data Register DAT Chinese name Data transfer register Register bit width 7 0 Offset 0x...

Page 91: ...of t gge 1 1 0 2nd Receive timeout There is at least one character in the FIFO But within 4 character time Operations including read and write operations Read receive FIFO 0 0 1 3 tad Transfer save d...

Page 92: ...parity if LCR 4 bit is 1 The bit is 0 If the LCR 4 bit is 0 transmit and check the parity The checkpoint is 1 4 eps 1 RW Parity bit selection 0 There are an odd number of 1s in each character includin...

Page 93: ...nect to RI input in loopback mode 1 RTSC 1 W RTS signal control bit 0 DTRC 1 W DTR signal control bit 11 3 7 Line Status Register LSR Chinese name Line status register Register bit width 7 0 Offset 0x...

Page 94: ...this register LSR 4 1 and LSR 7 are cleared and LSR 6 5 is writing data to the transmit FIFO Cleared according to the time LSR 0 judges the receive FIFO 11 3 8 MODEM status register MSR Chinese name M...

Page 95: ...ty and phase SPI can be controlled in wait mode Support boot from SPI The physical address of the SPI controller register is 0x1FE00220 Table 11 6 SPI controller address space distribution Address nam...

Page 96: ...s that there is an interrupt request write 1 to clear 6 wc Yaol 1 RW Write register overflow flag bit is 1 indicates that it has overflowed write 1 to clear 5 4 Rese 2 RW Keep 3 wffull 1 RW Write regi...

Page 97: ...mber selection frequency division coefficient is the same as spre spr combination 3 dual_io 1 RW Use dual I O mode with higher priority than fast read mode 2 fast_read 1 RW Use quick read mode 1 burst...

Page 98: ...arbiter and GPIO controller of the PCI controller Table 11 7 These registers are listed and Table 11 8 gives a detailed description of the registers The base address of this part of the register is 0...

Page 99: ...Window 2 controls the lower 32 bits 64 PCI_H t2_Sel_H PCI Window 2 controls the upper 32 bits 68 PXA b_C nf g PCIX arbiter configuration 6C PXA b_Status PCIX arbiter status 70 74 78 7C 80 Ch p C Yao...

Page 100: ...ad only 0 CR3C reserved 31 0 Keep Read only 0 Keep CR24 2C 30 34 38 reserved See table 11 3 CR50 54 58 5C 60 64 PCI_H t _Sel_ 0 Keep Read only 0 2 1 pc _ mg_s ze Read and write 2 b11 00 32 bits 10 64...

Page 101: ...Read only 0 CR80 Ch pc Yao nf g see section 2 6 CR90 Ch p Sample see section 2 6 CRA0 Ch p Sample see section 2 6 CRB0 PLL c Yao nf g see section 2 6 CRC0 PLL c Yao nf g see section 2 6 CRD0 C Yao Yi...

Page 102: ...of CPU window 3 0x0 CPU_WIN4_MMAP 0x3ff000a0 RW New base address of CPU window 4 0x0 CPU_WIN5_MMAP 0x3ff000a8 RW New base address of CPU window 5 0x0 CPU_WIN6_MMAP 0x3ff000b0 RW New base address of CP...

Page 103: ...indow 2 63 valid 47 0 addr 0x0 Slock3_addr 0x3ff00218 RW Lock address of lock window 3 63 valid 47 0 addr 0x0 Slock0_mask 0x3ff00240 RW Lock window mask 0 47 0 mask 0x0 Slock1_mask 0x3ff00248 RW Lock...

Page 104: ...ff00820 RW SCache0_perfcnt2 0x3ff00828 RO SCache0_perfctrl3 0x3ff00830 RW SCache0_perfcnt3 0x3ff00838 RO SCache1_perfctrl0 0x3ff00900 RW SCache1_perfcnt0 0x3ff00908 RO Page 131 Godson 3A3000 3B3000 Pr...

Page 105: ...ocessor core 1 Core1_IPI_Enalbe 0x3ff01104 RW IPI_Enalbe register of processor core 1 0x0 Core1_IPI_Set 0x3ff01108 WO IPI_Set register of processor core 1 Core1_IPI_Clear 0x3ff0110c WO IPI_Clear regis...

Page 106: ...ompare 0x3ff01368 RW Int Entry 0 31 0x3ff01400 RW 32 8 bit interrupt routing registers 0x0 Intisr 0x3ff01420 RO 32 bit interrupt status register Inten 0x3ff01424 RO 32 bit interrupt enable status regi...

Page 107: ...ature interrupt control register 7 0 Lo_gate0 low temperature threshold 0 below this temperature will generate an interrupt 8 8 Lo_en0 Low temperature interrupt enable 0 11 10 Lo_Sel0 Select the tempe...

Page 108: ...ct the temperature sensor input source for high temperature down conversion 2 46 44 Scale_freq2 frequency division value when frequency is reduced 55 48 Scale_gate3 High temperature threshold 3 over t...

Page 109: ...wid is met at the same time 63 awchannel_en enable trigger condition The trigger condition is AW_IN AWMASK AWCOND AWMASK CORE0_AWCOND1 0x3ff01810 RW The trigger condition of AW must be satisfied by bo...

Page 110: ...31 16 wstrb 32 wlast 33 wvalid 34 wready CORE0_WMASK0 0x3ff01848 RW CORE0 s AXI interface W trigger enable 0 setting the highest bit is the W channel trigger enable 49 0 wmask 63 wchannel_en Trigger...

Page 111: ...01898 RW CORE0_RCOND2 0x3ff018a0 RW CORE0_RMASK2 0x3ff018a8 RW Page 143 Godson 3A3000 3B3000 Processor User Manual Volume 1 139 TUD0_CONF0 0x3ff018e0 RW TUD0 configuration register 0 47 0 count_target...

Page 112: ...tion similar to AW CORE1_WMASK0 0x3ff01948 RW CORE1_WCOND1 0x3ff01950 RW CORE1_WMASK1 0x3ff01958 RW CORE1_WCOND2 0x3ff01960 RW CORE1_WMASK2 0x3ff01968 RW CORE1_BCOND0 0x3ff01970 RW CORE1 s AXI interfa...

Page 113: ...ger condition similar to AW CORE2_ARMASK0 0x3ff01a28 RW CORE2_ARCOND1 0x3ff01a30 RW CORE2_ARMASK1 0x3ff01a38 RW CORE2_WCOND0 0x3ff01a40 RW CORE2 s AXI interface W trigger condition similar to AW CORE2...

Page 114: ...on 0 setting CORE3_AWMASK0 0x3ff01b08 RW CORE3 AXI interface AW trigger enable 0 is set the highest bit is AW channel trigger enable The trigger condition is AW_IN AWMASK AWCOND AWMASK CORE3_AWCOND1 0...

Page 115: ...f01b98 RW CORE3_RCOND2 0x3ff01ba0 RW CORE3_RMASK2 0x3ff01ba8 RW Page 150 Godson 3A3000 3B3000 Processor User Manual Volume 1 146 TUD3_CONF0 0x3ff01be0 RW TUD3 configuration register 0 47 0 count_targe...

Page 116: ...r User Manual Volume 1 148 TUD5_CONF1 0x3ff01de8 RW TUD5 configuration register 1 2 0 DCDL_sel_signal 5 3 DCDL_sel_clock 8 6 signal_sel 11 9 clock_sel 18 12 reading_sel 19 counter_clock_sel 20 sticky...

Page 117: ...0x3ff01e88 RW HT0_RCOND1 0x3ff01e90 RW HT0_RMASK1 0x3ff01e98 RW HT0_RCOND2 0x3ff01ea0 RW HT0_RMASK2 0x3ff01ea8 RW HT1_AWCOND0 0x3ff01f00 RW HT1 AXI interface AW trigger condition 0 setting Page 154 Go...

Page 118: ...address window 0x0 CORE0_WIN7_BASE 0x3ff02038 RW First level crossbar address window 0x0 CORE0_WIN0_MASK 0x3ff02040 RW First level crossbar address window 0x0 CORE0_WIN1_MASK 0x3ff02048 RW First leve...

Page 119: ...crossbar address window 0x0 CORE1_WIN4_MASK 0x3ff02160 RW First level crossbar address window 0x0 CORE1_WIN5_MASK 0x3ff02168 RW First level crossbar address window 0x0 CORE1_WIN6_MASK 0x3ff02170 RW F...

Page 120: ...crossbar address window 0x0 CORE2_WIN7_MMAP 0x3ff022b8 RW First level crossbar address window 0x0 Page 159 Godson 3A3000 3B3000 Processor User Manual Volume 1 155 CORE3_WIN0_BASE 0x3ff02300 RW First...

Page 121: ...IN2_MASK 0x3ff02450 RW First level crossbar address window 0x0 EAST_WIN3_MASK 0x3ff02458 RW First level crossbar address window 0x0 EAST_WIN4_MASK 0x3ff02460 RW First level crossbar address window 0x0...

Page 122: ...OUTH_WIN2_MMAP 0x3ff02590 RW First level crossbar address window 0x0 SOUTH_WIN3_MMAP 0x3ff02598 RW First level crossbar address window 0x0 SOUTH_WIN4_MMAP 0x3ff025a0 RW First level crossbar address wi...

Page 123: ...ar address window 0x0 NORTH_WIN1_BASE 0x3ff02708 RW First level crossbar address window 0x0 NORTH_WIN2_BASE 0x3ff02710 RW First level crossbar address window 0x0 NORTH_WIN3_BASE 0x3ff02718 RW First le...

Page 124: ...n the software and hardware settings of the Loongson 3A3000 3B3000 processor compared with Loongson 3A1000 2000 the difference 13 1 Hardware modification guide 1 The original CORE_PLL_AVDD and DDR_PLL...

Page 125: ...core frequency For Godson 3A3000 3B3000A B C PMON must use L2 PLL as the main clock when configuring the frequency and 3A2000 Consistent 10 For the 3A2H motherboard you need to remove the pull up res...

Page 126: ...nts of jr rx and rx which are not register 31 in all assembly codes to jr 31 6 Use code similar to 3B1500 to configure processor core memory and node PLL 7 Use the memory controller configuration and...

Page 127: ...n back to the Cache the second is that all The unlock operation in the synchronous operation shared among different cores is implemented using LL SC instructions Consistent with 3A2000 8 Do not use th...

Page 128: ...4 29 2020 Loongson 3A3000 3B3000 Processor User Manual 128 166...

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