4/29/2020
Loongson 3A3000 / 3B3000 Processor User Manual
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1)
The other registers in the setting register except SEL_PLL_ * and SOFT_SET_PLL, that is, these two
The register is written as 0 during the setting process;
2)
Other register values remain unchanged, set SOFT_SET_PLL to 1;
3)
Wait for the lock signal LOCKED_ * in the register to be 1;
4)
Set SEL_PLL_ * to 1, and the corresponding clock frequency will be switched to the frequency set by the software.
In 3A3000 / 3B3000, two different PLLs can be used
L1 L2
se al_m
耀
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PLL
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Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
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Table 2- 13 Chip node and processor core software frequency multiplication setting register (physical address 0x1fe001b0)
Bit field
Field name
access
Reset value
description
0
SEL_PLL_NODE
RW
0x0
Node clock non-software bypass entire
PLL
1
SEL_PLL_NODE
RW
0x0
Core clock non-software bypass entire PLL
2
SOFT_SET_PLL
RW
0x0
Allow software to set PLL
3
BYPASS_L1
RW
0x0
Bypass L1 PLL
15: 4
-
RW
0x0
-
16
LOCKED_L1
R
0x0
Whether L1 PLL is locked
17
LOCKED_L2
R
0x0
Whether L2 PLL is locked
18:17-
R
0x0
-
19
PD_L1
RW
0x0
Turn off L1 PLL
20
PD_L2
RW
0x0
Turn off L2 PLL
twenty one
twenty two
Serial_mode
RW
0x0
0: Select L1 PLL as the main clock
1: Select L2 PLL as the main clock
twenty three
Serial_mode3
RW
0x0
0: Use NODE clock as the core clock
1: Select CORE clock as the core clock
25:24-
RW
-
31:26 L1_DIV_REFC
RW
0x1
L1 PLL input parameters
40:32 L1_DIV_LOOPC
RW
0x1
L1 PLL input parameters
41
47:42 L1_DIV_OUT
RW
0x1
L1 PLL input parameters
50:48 L2_DIV_REFC
RW
0x1
L2 PLL input parameters
53:51
63:54 L2_DIV_LOOPC
RW
0x1
L2 PLL input parameters
69:64 L2_DIV_OUT
RW
0x1
L2 PLL input parameters
Only one bit is required
96
BBGEN_enable
RW
0x0
Bias enable
97
BBMUX_first
RW
0x0
Set to switch voltage mode first
99:98 BBMUX_SEL_0
RW
0x0
BBMUX_SEL_0 setting value
101: 100 BBGEN_feedback
RW
0x0
Disable BBGEN feedback signal
107: 104 BBGEN_vbbp_val
WO
0x0
Setting value of Vbbp
111: 108 BBGEN_vbbn_val
WO
0x0
Setting value of Vbbn
123: 122 BBMUX_SEL_1
RW
0x0
BBMUX_SEL_1 setting value
125: 124 BBMUX_SEL_2
RW
0x0
BBMUX_SEL_2 setting value
