Lenze EVS9321-CS, Operating Instructions Manual

Page: 101 / 189

Configuration
8-12
BA9300SU EN 2.1
8.4 Description of function blocks
Function blocks
Function block Description CPU time used in basic configuration C0005 p
[
µ
s]
1000 4000 5000 6000 7000 20 21
ABS1 Absolute value generator 5
• •
ADD1 Addition block 9
•
AIF-OUT Field bus 60
• • • • •
AIN1 Analog input X6/1, X6/2 11
• • • • • • •
AIN2 Analog input X6/3, X6/4 29
• • • • • • •
AND1 Logic AND, block1
7
• •
AND2 Logic AND, block2
• •
AND3 Logic AND, block3
• •
AND4 Logic AND, block4
•
AND5 Logic AND, block5
AND6 Logic AND, block6
AND7 Logic AND, block7
ANEG1 Analog inverter 1 4
• • • • • • •
ANEG2 Analog inverter 2 4
•
AOUT1 Analog output X6/62 13
• • • • • • •
AOUT2 Analog output X6/63 13
• • • • • • •
ARIT1 Arithmetic block 1 12
• •
ARIT2 Arithmetic block 2 12
ARITPH1 32-bit arithmetic block 15
ASW1 Analog changeover 1 4
• • • •
ASW2 Analog changeover 2 4
• •
ASW3 Analog changeover 3 4
• •
ASW4 Analog changeover 4 4
• •
BRK Trigger holding brake 17
CAN-OUT System bus 60
• • • • •
CMP1 Comparator 1 15
• • • • • • •
CMP2 Comparator 2 15
• •
CMP3 Comparator 3 15
•
CONV1 Conversion 9
CONV2 Conversion 9
CONV3 Conversion 9
•
CONV4 Conversion 9
CONV5 Conversion 9
•
CONV6 Conversion 9
•
CONVPHA1 32 bit conversion 6
CONVPHPH1 32 bit conversion 80
CONVPP1 32 bit / 16 bit conversion 55
DB1 Dead band 8
•
DCTRL Device control -
• • • • • • •
DFIN Digital frequency input 6
• • • • • •
DFOUT Digital frequency output 38
• • • • • • •
DFRFG1 Digital frequency ramp generator 44
DFSET Digital frequency processing 93
• • • •
DIGDEL1 Binary delay element 1 10
DIGDEL2 Binary delay element 2 10
DIGIN Input terminals X5/E1...X5/E5 -
• • • • • • •
DIGOUT Output terminals X5/A1...X5/A4 -
• • • • • • •
DT1-1 Differential element 13
FCNT1 Piece counter 11