JDS Uniphase SmartClass E1, User Manual

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Appendix B Specifications
Datacom specifications
118 SmartClass E1 Tester User’s Guide
Datacom specifications
The following sections contain specifications related to the Datacom testing
option.
Supported interface
standards
Table 45 lists the supported Datacom test interfaces and circuits.
About pin assignments
All of the signals necessary for the supported interfaces are mapped to pins on
the universal Datacom connector. The following sections describe the pin
assignments for the supported interfaces.
RS-232/V.24 pin assignments
Table 46 lists pin assignments for the RS-232/V.24 interface.
Table 45 Datacom interface specifications
Interface Standard Supported Circuits
RS-232/V.24 BA, BB, CA, CB, DD, CF, DB, DD, LL, RL, CD, DA,
and TM
EIA-530 EIA-422-B: BA, BB, CA, CB, CC, CD, CF, DA, DB,
and DD
EIA-423-B: LL, RL, and TM.
RS-449/V.36 EIA-422-B: SD, RD, RS, CS, DM, TR, RR, RT, ST,
and TT
EIA-423-B: LL, RL, and TM.
V.35 Balanced clock and data circuits
EIA-232/V.24 control circuits
306: SCT, SCTE, SCR, SD, and RD
V.35: 103, 104, 114, and 115
V.28: 105, 106, 107, and 109
X.21 V.11: R, I, S, T, C
a
, and X
b
a. With cable CB-44390 or CB-44346
b. With cable CB-44391 or CB-44345
Co-directional Timing AMI with block violation for Octet timing
Contra-directional Timing
and Centralized Timing Data - AMI with 100% duty cycle
Clock - AMI with 50% duty cycle
Table 46 RS-232/V.24 pin assignments
Pin Signal Description Signal Source CCITT Circuit
1 Signal Ground N/A 102
2 Transmitted Data DTE 103
3 Received Data DCE 104
4 Request to Send DTE 105
5 Clear to send DCE 106
6 Data Set Ready DCE 107
7 Signal Ground N/A 102