REL 1.0
Page 42 of 53
Cyclone V SoC Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No
Signal Name
Cyclone V SoC
Ball Name/
Pin Number
Signal Type/
Termination
Description
73
FPGA_JTAG_TCK
TCK/
AB5
I, 3.3V CMOS
JTAG Test Clock.
74
FPGA_AG21_SEIO4A
FPGA IO/
AG21
IO, 2.5V CMOS Single ended bidirectional signal.
75
FPGA_JTAG_TDO
TDO/
Y9
O, 3.3V CMOS
JTAG Test Data output.
76
FPGA_AH21_SEIO4A
FPGA IO/
AH21
IO, 2.5V CMOS Single ended bidirectional signal.
77
FPGA_JTAG_TMS
TMS/
AC7
I, 3.3V CMOS
JTAG Test mode select.
78
FPGA_AG26_SEIO4A
FPGA IO/
AG26
IO, 2.5V CMOS Single ended bidirectional signal.
79
FPGA_JTAG_TDI
TDI/
W10
I, 3.3V CMOS
JTAG Test data input.
80
FPGA_AH26_SEIO4A
FPGA IO/
AH26
IO, 2.5V CMOS Single ended bidirectional signal.