REL 1.0
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Cyclone V SoC Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
From FPGA High Speed Transceiver:
PCIe Gen2.0 x 4 Ports through Cyclone V SoC Hard Block
SATA x 1 Port (Soft IP)
From FPGA (Soft IP):
LVDS LCD x 2 Ports
AC97/SSI Audio x 1 Port
PWM x 1 Port
8 Single Ended GPIOs/LPC Interface
Expansion Connector Interfaces (from FPGA)
General Purpose Clock Inputs (2 LVDS/2 SE)
General Purpose Clock Outputs (1 LVDS/2 SE)
9 TX LVDS Pairs/18 SE IOs
11 RX LVDS Pairs/22 SE IOs
5 Single Ended IOs
SMBUS/2 SE IOs
FPGA JTAG
General Specification
Power Supply
:
5V, 2A
Form Factor
:
70mm X 70mm (Qseven R2.0 Specification)
Note: If the FPGA interfaces available in the Qseven edge are not used for Qseven compliance requirement, same
interface pins can be used for custom Industrial/Networking interface requirements.
Note: iWave supports different Soft IPs for Cyclone V FPGA. Please contact iWave for more details.
