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Cyclone V SoC Qseven SOM Hardware User Guide

iWave Systems Technologies Pvt. Ltd.

ARCHITECTURE AND DESIGN

This section provides detailed information about the Cyclone V SoC Qseven SOM Features and Hardware

architecture with high level block diagram. Also this section provides detailed information about Qseven edge

connector & Expansion connector pin assignment and usage.

2.1

Cyclone V SoC Qseven SOM Block Diagram

iW-RainboW-G17M-Cyclone V SoC Qseven SOM Block Diagram

QSEVEN

PCB Edge

Connector

(230Pin)

80 Pin

Expansion
connector

DDR3 RAM

(512MB)

DDR3 (32bit)

QSPI Flash

(16MB)

QSPI

RTC

Controller

Ethernet

PHY

USB PHY

USB 2.0 Hub

(4Port)

Gbit Ethernet

RGMII

Hard Processor System

(Dual-core

ARM® Cortex™-A9

MP Core processor)

FPGA

PCIe x 4 Port

SATA x 1 Port

UTMI

I2C

Power IN

(Optional)

Power

Regulators

Power to
Peripherals

HPS JTAG

JTAG

USB Host

FPGA JTAG

JTAG

SMBUS/2 SE IOs

DDR3 for ECC

DDR3 ECC (8bit)

EEPROM

(Optional)

I2C

8 Single Ended IOs/LPC Interface

9 TX LVDS Pairs/18 SE IOs

Cyclone V SX - SoC FPGA

11 RX LVDS Pairs/22 SE IOs

General Purpose Clock Inputs (2 LVDS/2 SE)

SD/MMC (8bit)

SPI (with 2 Chip selects)

Debug UART

2nd UART

CAN

I2Cx 2 Ports

Micro SD

Connector

5 Single Ended IOs

WDOG

PWM

General Purpose Clock Outputs (1 LVDS/2 SE)

FPGA AS

Header

(Optional)

AS Interface

SATA 2

Port* (Optional)

SDRAM

Controller

SPIM0

I2C0, I2C1

UART0

UART1

CAN1

GPIO

USB1

JTAG

EMAC1

SD/MMC

CH0
CH1
CH2
CH3

CH5
CH4

AC97/I2S x 1 Port

FPGA IOs

(2.5V Differential /

2.5V Single Ended)

FPGA IOs

(3.3V Single

Ended)

DDR3 RAM

(256MB)

EPCQ Flash

(Optional)

DDR3 (16bit)

QSPI Flash

(Optional)

DDR3 Controller

(Soft IP)

JTAG

FPGA Dedicated

Clock IOs

(2.5V Differential /

2.5V Single Ended)

LVDS LCD (24bpp) x 2 Port

LCD (Soft IP)

2.5V Differential

SMBUS (Soft IP)

3.3V Single Ended

* If SATA 2

Port is needed, PCIe x 2 port only can be supported

QSPI

I2C0

Active Serial

AC97/I2S(Soft IP)

3.3V Single Ended

Figure 1

Cyclone V SoC Qseven SOM Block Diagram

Summary of Contents for iW-RainboW-G17M

Page 1: ...REL 1 0 Page 1 of 53 Cyclone V SoC Qseven SOM Hardware User Guide iWave Systems Technologies Pvt Ltd iW RainboW G17M Cyclone V SoC Qseven SOM Hardware User Guide...

Page 2: ...E This document contains proprietary material for the sole use of the intended recipient s Do not read this document if you are not the intended recipient Any review use distribution or disclosure by...

Page 3: ...able for the silicon errata and associated issues Trademarks All registered trademarks and product names mentioned in this publication are used for identification purposes only Certification iWave Sys...

Page 4: ...5 2 HPS QSPI Flash 17 2 5 3 HPS EEPROM Optional 17 2 5 4 FPGA DDR3 SDRAM 17 2 5 5 FPGA Configuration Flash Optional 17 2 6 Other Features 18 2 6 1 RTC Controller 18 2 6 2 HPS JTAG Header 18 2 6 3 FPG...

Page 5: ...liance 46 3 2 4 Electrostatic Discharge 46 3 3 Mechanical Characteristics 47 3 3 1 Qseven SOM Mechanical Dimensions 47 3 3 2 Guidelines to insert the Qseven SOM into Carrier board 49 4 ORDERING INFORM...

Page 6: ...ew 48 Figure 14 Mechanical dimension of Qseven SOM Side View 48 Figure 15 Qseven Module Insertion procedure 49 Figure 16 Silk Screen Top View 51 Figure 17 Silk Screen Bottom View 52 Figure 18 Cyclone...

Page 7: ...ctor of 70mm x70mm and have specified pin outs based on the high speed MXM system connector that has a standardized pin out regardless of the vendor A single ruggedized MXM connector provides the carr...

Page 8: ...nt Interconnect Express PWM Pulse Width Modulation QSPI Quad Serial Peripheral Interface RAM Random Access Memory RGMII Reduced Gigabit Media Independent Interface ROM Read Only Memory RTC Real Time C...

Page 9: ...output CMOS Complementary Metal Oxide Semiconductor Signal LVDS Low Voltage Differential Signal DIFF Differential Signal OD Open Drain Signal OC Open Collector Signal PU Pull Up PD Pull Down NA Not Ap...

Page 10: ...me is SDMMC_D0 For SoC HPS Signals If HPS pin functionality name and pad name is different Signal name is mentioned as HPS_Functionality Name SoC Pad Name Example HPS_USB1_D0 RGMII0_TXD0 In this signa...

Page 11: ...SE IOs DDR3 for ECC DDR3 ECC 8bit EEPROM Optional I2C 8 Single Ended IOs LPC Interface 9 TX LVDS Pairs 18 SE IOs Cyclone V SX SoC FPGA 11 RX LVDS Pairs 22 SE IOs General Purpose Clock Inputs 2 LVDS 2...

Page 12: ...oot Clock Setting Switch Optional Reset Switch Memory 512MB HPS DDR3 RAM with ECC Expandable HPS QSPI Flash 16MB HPS EEPROM Optional 256MB FPGA DDR3 RAM Expandable FPGA Configuration Flash Optional Ot...

Page 13: ...A General Purpose Clock Inputs 2 LVDS 2 SE General Purpose Clock Outputs 1 LVDS 2 SE 9 TX LVDS Pairs 18 SE IOs 11 RX LVDS Pairs 22 SE IOs 5 Single Ended IOs SMBUS 2 SE IOs FPGA JTAG General Specificat...

Page 14: ...ility for the system designers and helps to lower the system cost and power consumption This improved logic integration with increased bandwidth capacity which is ideal for cost sensitive high end app...

Page 15: ...The Cyclone V SoC Boot ROM code reads the boot information register to read the boot select bsel and clock select csel values to determine the boot source and to set up the clock manager The bsel and...

Page 16: ...GA HPS to FPGA bridge OFF OFF SPI or Quad SPI Flash Memory ON ON ON High OFF Low 2 4 2 Boot Clock Switch Optional Cyclone V SoC Qseven SOM optionally supports two positions Boot Clock Switch SW3 which...

Page 17: ...Optional Cyclone V SoC Qseven SOM supports 256Mbit EEPROM memory as optional configuration storage EEPROM is connected to the HPS Block of the Cyclone V SoC through I2C0 Interface and operating under...

Page 18: ...power off condition this device will take power from Qseven Edge VCC_RTC coin cell power input Pin 193 2 6 2 HPS JTAG Header A customized 20 pin ARM JTAG connector is available in Cyclone V SoC Qseve...

Page 19: ...age 3 HPS_TRST I 3 3V CMOS 10K PU JTAG test reset signal 4 GND Power Ground 5 HPS_TDI I 3 3V CMOS 10K PU JTAG test data input 6 GND Power Ground 7 HPS_TMS I 3 3V CMOS 10K PU JTAG test mode select 8 GN...

Page 20: ...Pins 10 Connector Part GRPB052MWCN RC from Sullins Connector Solutions Mating Connector LPPB052CFFN RC from Sullins Connector Solutions Table 5 FPGA JTAG Header Pin Assignment Pin No Signal Name Signa...

Page 21: ...C from Sullins Connector Solutions Mating Connector LPPB052CFFN RC from Sullins Connector Solutions Table 6 FPGA AS Header Pin Assignment Pin No Signal Name Signal Type Termination Description 1 FPGA_...

Page 22: ...e 2 GND Power Ground The below table provides the power IN circuit BOM which can be used to mount power IN circuit for standalone Cyclone V SoC Qseven SOM power up Table 8 Power IN Connector BOM Sl No...

Page 23: ...ge connector has standard pin out as per Qseven Specification 2 0 The interfaces which are available at Qseven edge connector are listed in the following sections Figure 8 Qseven PCB Edge Connector Nu...

Page 24: ...function Note The same interface is shared with On SOM Micro SD Slot Debug UART interface As per Qseven Specification JTAG and UART0 interface pins are multiplexed to same pins for debugging purpose...

Page 25: ...4 lane configuration SATA interface Qseven Edge connector has one SATA interface with speed up to 3 0 Gbps Gen2 from FPGA Soft IP This can be used to interface with different Hard disk drives Note If...

Page 26: ...GPHY_LINK_LED 2 NA O 3 3V CMOS Gigabit Ethernet link status LED Note Same signal is also connected to Qseven edge connector 7th 13th pins So use only in one place 9 GBE_MDI1 GPHY_BTXRXM NA IO DIFF Gig...

Page 27: ...ed Note This Pin is connected to Cyclone V HPS GPI12 through Voltage translator 21 SLP_BTN NC 22 LID_BTN NC 23 GND GND Power Ground 24 GND GND Power Ground 25 GND GND Power Ground 26 PWGIN SOM_PWREN N...

Page 28: ...t pin 44 SDIO_LED HPS_GPIO9 RG MII0_TX_CTL RGMII0_TX_CT L C6 O 3 3V CMOS SD MMC card indication LED 45 SDIO_CMD HPS_SDMMC_C MD SDMMC_CMD D14 IO 3 3V CMOS SD MMC card command line 46 SDIO_WP HPS_GPIO48...

Page 29: ...ns 63 HDA_BITCLK I2S_CLK FPGA_U9_AC97 _I2S_CLK FPGA IO U9 O 3 3V CMOS Audio transmit clock line 64 SMB_ALERT NC 65 HDA_SDI I2S_SDI FPGA_U10_AC9 7_I2S_SDI FPGA IO U10 I 3 3V CMOS Audio transmit data li...

Page 30: ...e for USB port2 port3 86 USB_0_1_OC USB_0_1_OC NA I 3 3V CMOS Over current sense for USB port0 port1 87 USB_P3 USB_HUBP3_D M NA IO DIFF USB Host port3 data negative 88 USB_P2 USB_HUBP2_D M NA IO DIFF...

Page 31: ...differential pair2 positive 109 eDP0_TX2 LVDS_A2 FPGA_AG20_LV DS_A2N FPGA IO AG20 O 2 5V LVDS LVDS primary channel differential pair2 negative 110 eDP1_TX2 LVDS_B2 FPGA_AE22_LV DS_B2N FPGA IO AE22 O 2...

Page 32: ...d 126th pin 126 eDP0_HPD LVDS_BLC_ DAT HPS_I2C1_SDA TRACE_D2 TRACE_D2 A21 IO 3 3V OD 4 7K PU I2C1 data signal Note Same signal is also connected to Qseven edge connector 62th 125th pins 127 GP2_I2C_CL...

Page 33: ...146 RSVD NC 147 GND GND Power Ground 148 GND GND Power Ground 149 DP_LANE0 TMDS_LANE 2 NC 150 HDMI_CTRL_ DAT NC 151 DP_LANE0 TMDS_LANE 2 NC 152 HDMI_CTRL_ CLK NC 153 DP_HDMI_H PD NC 154 RSVD2 NC 155 P...

Page 34: ...PCIE2_RX FPGA_V1_PCIe2 _RXN GXB_RX_L2N V1 I DIFF PCI Express channel 2 receive Input differential pair negative 171 UART0_TX HPS_UART1_TX I2C0_SCL I2C0_SCL B16 O 3 3V CMOS Data UART transmit data lin...

Page 35: ...IO 3 3V CMOS General Purpose Input Output This Pin is Connected to FPGA IO 190 LPC_FRAME GPIO5 FPGA_Y11_SEIO 3A FPGA IO Y11 IO 3 3V CMOS General Purpose Input Output This Pin is Connected to FPGA IO 1...

Page 36: ...S C23 I 3 3V CMOS JTAG Test Mode Select 211 VCC VCC_5V NA I 5V Power Input Supply Voltage 212 VCC VCC_5V NA I 5V Power Input Supply Voltage 213 VCC VCC_5V NA I 5V Power Input Supply Voltage 214 VCC VC...

Page 37: ...ected set of interfaces as per Qseven standard All the effort is made in Cyclone V SoC Qseven SOM design to provide maximum interfaces of Cyclone V SoC to the carrier board by adding an Expansion conn...

Page 38: ...DS Pairs Expansion connector supports 11 General purpose receive LVDS pairs to Cyclone V FPGA If Receive LVDS Pairs are not used it can be used as 22 single ended Input output signals from Cyclone V F...

Page 39: ...IO AG9 O 2 5V LVDS Transmit output differential pair positive 10 FPGA_AG28_DFIO4A_TXB77P FPGA IO AG28 O 2 5V LVDS Transmit output differential pair positive 11 GND Power Ground 12 GND Power Ground 13...

Page 40: ...FPGA IO AG13 I 2 5V LVDS Receive input differential pair positive 34 FPGA_AD17_DFIO4A_RXB54P FPGA IO AD17 I 2 5V LVDS Receive input differential pair positive 35 GND Power Ground 36 GND Power Ground...

Page 41: ...PGA IO Y13 I 2 5V LVDS Receive clock input differential pair positive 58 FPGA_Y15_DFCLKIN3P4A_RXB5 5P FPGA IO Y15 I 2 5V LVDS Receive clock input differential pair positive 59 GND Power Ground 60 GND...

Page 42: ...IO AG21 IO 2 5V CMOS Single ended bidirectional signal 75 FPGA_JTAG_TDO TDO Y9 O 3 3V CMOS JTAG Test Data output 76 FPGA_AH21_SEIO4A FPGA IO AH21 IO 2 5V CMOS Single ended bidirectional signal 77 FPGA...

Page 43: ...SOM is designed to work with VCC input power rail from Qseven Edge connector Optionally we can use On SOM Power In connector to feed VCC which can be used only for standalone power up Cyclone V SoC Qs...

Page 44: ...n Value T1 VCC_RTC rise time to VCC rise time 0 ms T2 VCC rise time to PWGIN rise time 0 ms T3 PWGIN fall time to VCC fall time 0 ms T4 VCC fall time to VCC_RTC fall time 0 ms 3 1 3 Power Consumption...

Page 45: ...tion For more information on Thermal solution Heat spreader refer the following section 3 2 2 Heat Spreader For any highly integrated System On Modules thermal design is very important factor As IC s...

Page 46: ...ompliance iWave s Cyclone V SoC Qseven SOM is designed by using RoHS compliant components and manufactured on lead free production process 3 2 4 Electrostatic Discharge iWave s Cyclone V SoC Qseven SO...

Page 47: ...specification Revision 2 0 The size of the PCB will be 70 mm x 70 mm x 1 2mm as per Qseven Specification Qseven SOM mechanical dimension is shown below Please refer the Qseven Specification Revision 2...

Page 48: ...View Cyclone V SoC Qseven SOM PCB thickness is 1 2mm top side maximum height component is Power Inductors 4 5mm and bottom side maximum height component is expansion connector 4 30mm followed by Crys...

Page 49: ...ector at an angle of 45 as shown below in the first photo Check the Notch position of Qseven module is proper while inserting Once the Qseven module is inserted to the MXM connector properly press the...

Page 50: ...pansion Industrial iW G17M Q702 3E512M S000G BIB With 5CSXFC6C6U23I7N SoC 512MB DDR3 for HPS 256MB DDR3 for FPGA SD storage with Boot code With Expansion Industrial Cyclone V SoC with 40K LUT based Qs...

Page 51: ...5 APPENDIX I 5 1 Cyclone V SoC Qseven SOM Silk Screen Cyclone V SoC Qseven SOM s PCB silkscreen top view and bottom view for Optional Feature s Identifier are shown in the below Figures This will be u...

Page 52: ...REL 1 0 Page 52 of 53 Cyclone V SoC Qseven SOM Hardware User Guide iWave Systems Technologies Pvt Ltd Figure 17 Silk Screen Bottom View...

Page 53: ...all necessary interfaces on board connectors to validate complete Qseven supported features iWave Systems supports iW RainboW G17D Cyclone V SoC Qseven Development Platform with Cyclone V SoC Qseven...

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