iWave iW-RainboW-G17M, Hardware User'S Manual

Page: 30 / 53

REL 1.0
Page 30 of 53
Cyclone V SoC Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No.
Qseven Edge
Connector
Pin Name
Signal Name
Cyclone V SoC
Ball Name/
Pin Number
Signal Type/
Termination
Description
77 /
US - - - NC.
78 /
US - - - NC.
79 USB_6_7_OC
# - - - NC.
80 USB_4_5_OC
# USB_4_5_OC NA I, 3.3V CMOS Over current sense for USB port 4
& 5.
81 USB_P5-/
USB_SSTX1- - - - NC.
82 USB_P4-/
USB_SSRX1- USB_HUBP4_D
M NA IO, DIFF USB Host port4 data negative.
83 /
US - - - NC.
84 /
US USB_HUBP4_DP NA IO, DIFF USB Host port4 data positive.
85 USB_2_3_OC
# USB_2_3_OC NA I, 3.3V CMOS Over current sense for USB port2 &
port3.
86 USB_0_1_OC
# USB_0_1_OC NA I, 3.3V CMOS Over current sense for USB port0 &
port1.
87 USB_P3- USB_HUBP3_D
M NA IO, DIFF USB Host port3 data negative.
88 USB_P2- USB_HUBP2_D
M NA IO, DIFF USB Host port2 data negative.
89 USB_HUBP3_DP NA IO, DIFF USB Host port3 data positive.
90 USB_HUBP2_DP NA IO, DIFF USB Host port2 data positive.
91 USB_CC - - - NC.
92 USB_ID - - - NC.
93 USB_P1- - - - NC.
94 USB_P0- USB_HUBP1_D
M NA IO, DIFF USB Host Port1 d ata negative.
95 - - - NC.
96 USB_HUBP1_DP NA IO, DIFF USB Host Port1 data positive.
97 GND GND - Power Ground.
98 GND GND - Power Ground.
99 e/
FPGA_AH23_LV
DS_A0P FPGA IO/
AH23 O, 2.5V LVDS LVDS primary channel differential
pair0 positive.
100 e/
FPGA_AA19_LV
DS_B0P FPGA IO/
AA19 O, 2.5V LVDS LVDS secondary channel
differential pair0 positive.