REL 1.0
Page 19 of 53
Cyclone V SoC Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Table 4: HPS JTAG Header Pin Assignment
Pin
No
Signal Name
Signal Type/
Termination
Description
1
VCC_3V3
O, 3.3V Power
VREF reference Voltage.
2
VCC_3V3
O, 3.3V Power
Supply Voltage.
3
HPS_TRST
I, 3.3V CMOS/
10K PU
JTAG test reset signal.
4
GND
Power
Ground.
5
HPS_TDI
I, 3.3V CMOS/
10K PU
JTAG test data input.
6
GND
Power
Ground.
7
HPS_TMS
I, 3.3V CMOS/
10K PU
JTAG test mode select.
8
GND
Power
Ground.
9
HPS_TCK
I, 3.3V CMOS/
1K PD
JTAG test Clock.
10
GND
Power
Ground.
11
-
-
NC.
12
GND
Power
Ground.
13
HPS_TDO
O, 3.3V CMOS
JTAG test data output.
14
GND
Power
Ground.
15
RSTBTN
I, 3.3V CMOS
Reset Signal.
16
GND
Power
Ground.
17
-
-
NC.
18
GND
Power
Ground.
19
-
-
NC.
20
GND
Power
Ground.