iWave iW-RainboW-G17M, Hardware User'S Manual

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REL 1.0
Page 31 of 53
Cyclone V SoC Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No.
Qseven Edge
Connector
Pin Name
Signal Name
Cyclone V SoC
Ball Name/
Pin Number
Signal Type/
Termination
Description
101 eDP0_TX0-/
LVDS_A0- FPGA_AH22_LV
DS_A0N FPGA IO/
AH22 O, 2.5V LVDS LVDS primary channel differential
pair0 negative.
102 eDP1_TX0-/
LVDS_B0- FPGA_AA18_LV
DS_B0N FPGA IO/
AA18 O, 2.5V LVDS LVDS secondary channel
differential pair0 negative.
103 e/
FPGA_AG18_LV
DS_A1P FPGA IO/
AG18 O, 2.5V LVDS LVDS primary channel differential
pair1 positive.
104 e/
FPGA_AE20_LV
DS_B1P FPGA IO/
AE20 O, 2.5V LVDS LVDS secondary channel
differential pair1 positive.
105 eDP0_TX1-/
LVDS_A1- FPGA_AH18_LV
DS_A1N FPGA IO/
AH18 O, 2.5V LVDS LVDS primary channel differential
pair1 negative.
106 eDP1_TX1-/
LVDS_B1- FPGA_AD20_LV
DS_B1N FPGA IO/
AD20 O, 2.5V LVDS LVDS secondary channel
differential pair1 negative.
107 e/
FPGA_AF20_LV
DS_A2P FPGA IO/
AF20 O, 2.5V LVDS LVDS primary channel differential
pair2 positive.
108 e/
FPGA_AD23_LV
DS_B2P FPGA IO/
AD23 O, 2.5V LVDS LVDS secondary channel
differential pair2 positive.
109 eDP0_TX2-/
LVDS_A2- FPGA_AG20_LV
DS_A2N FPGA IO/
AG20 O, 2.5V LVDS LVDS primary channel differential
pair2 negative.
110 eDP1_TX2-/
LVDS_B2- FPGA_AE22_LV
DS_B2N FPGA IO/
AE22 O, 2.5V LVDS LVDS secondary channel
differential pair2 negative.
111 LVDS_PPEN FPGA_Y8_LVDS_
PPEN FPGA IO/
Y8 O, 3.3V CMOS LVDS LCD panel power enable
control.
112 LVDS_BLEN FPGA_W8_LVDS
_BLEN FPGA IO/
W8 O, 3.3V CMOS LVDS LCD panel backlight enable
control.
113 e/
FPGA_AG19_LV
DS_A3P FPGA IO/
AG19 O, 2.5V LVDS LVDS primary channel differential
pair3 positive.
114 e/
FPGA_AF22_LV
DS_B3P FPGA IO/
AF22 O, 2.5V LVDS LVDS secondary channel
differential pair3 positive.
115 eDP0_TX3-/
LVDS_A3- FPGA_AH19_LV
DS_A3N FPGA IO/
AH19 O, 2.5V LVDS LVDS primary channel differential
pair3 negative.
116 eDP1_TX3-/
LVDS_B3- FPGA_AF21_LV
DS_B3N FPGA IO/
AF21 O, 2.5V LVDS LVDS secondary channel
differential pair3 negative.
117 GND GND - Power Ground.
118 GND GND - Power Ground.
119 e/
LVDS_A_CLK
+ FPGA_AG14_LV
DS_ACLKP FPGA IO/
AG14 O, 2.5V LVDS LVDS primary channel differential
clock positive.
120 e/
LVDS_B_CLK +
FPGA_AG23_LV
DS_BCLKP FPGA IO/
AG23 O, 2.5V LVDS LVDS secondary channel
differential clock Positive.
121 eDP0_AUX-/
LVDS_A_CLK- FPGA_AH13_LV
DS_ACLKN FPGA IO/
AH13 O, 2.5V LVDS LVDS primary channel differential
clock negative.