Thermal Specifications
90
6.3.1.2
Processor Thermal Data Sample Rate and Filtering
The Digital Thermal Sensor (DTS) provides an improved capability to monitor device
hot spots, which inherently leads to more varying temperature readings over short time
intervals. The DTS sample interval range can be modified, and a data filtering algorithm
can be activated to help moderate this. The DTS sample interval range is 82us (default)
to 20 ms (max). This value can be set in BIOS.
To reduce the sample rate requirements on PECI and improve thermal data stability vs.
time the processor DTS also implements an averaging algorithm that filters the
incoming data. This is an alpha-beta filter with coefficients of 0.5, and is expressed
mathematically as: Current_filtered_temp = (Previous_filtered_temp / 2) +
(new_sensor_temp / 2). This filtering algorithm is fixed and cannot be changed. It is on
by default and can be turned off in BIOS.
Host controllers should utilize the min/max sample times to determine the appropriate
sample rate based on the controller's fan control algorithm and targeted response rate.
The key items to take into account when settling on a fan control algorithm are the DTS
sample rate, whether the temperature filter is enabled, how often the PECI host will
poll the processor for temperature data, and the rate at which fan speed is changed.
Depending on the designer’s specific requirements the DTS sample rate and alpha-beta
filter may have no effect on the fan control algorithm.
6.3.2
PECI Specifications
6.3.2.1
PECI Device Address
The PECI device address for socket 0 is 0x30 and socket 1 is 0x31. Please note that
each address also supports two domains (Domain0 and Domain1). For more
information on PECI domains, please refer to the Platform Environment Control
Interface (PECI) Specification.
6.3.2.2
PECI Command Support
PECI command support is covered in detail in Platform Environment Control Interface
Specification. Please refer to this document for details on supported PECI command
function and codes.
Figure 6-9. Conceptual Fan Control Diagram of PECI-based Platforms
Fan Speed
(RPM )
(not intended to depict actual implementation)
M ax
M in
Temperature
PECI = -10
PECI = -20
TCC Activation
Temperature
T
CONTROL
Setting
PECI = 0
Fan Speed
(RPM )
(not intended to depict actual implementation)
M ax
M in
Temperature
PECI = -10
PECI = -20
TCC Activation
Temperature
T
CONTROL
Setting
PECI = 0
Summary of Contents for L5310 - Cpu Xeon Quad-Core Lv 1.6Ghz Fsb1066Mhz 8M Fc-Lga6 Tray
Page 1: ...318590 005 Dual Core Intel Xeon Processor 5200 Series Datasheet August 2008...
Page 8: ...8 Dual Core Intel Xeon Processor 5200 Series Datasheet...
Page 14: ...14...
Page 92: ...Thermal Specifications 92...
Page 98: ...Features 98...
Page 102: ...Boxed Processor Specifications 102 Figure 8 4 Top Side Board Keepout Zones Part 1...
Page 103: ...103 Boxed Processor Specifications Figure 8 5 Top Side Board Keepout Zones Part 2...
Page 104: ...Boxed Processor Specifications 104 Figure 8 6 Bottom Side Board Keepout Zones...
Page 105: ...105 Boxed Processor Specifications Figure 8 7 Board Mounting Hole Keepout Zones...
Page 106: ...Boxed Processor Specifications 106 Figure 8 8 Volumetric Height Keep Ins...
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