Intel L5310 - Cpu Xeon Quad-Core Lv 1.6Ghz Fsb1066Mhz 8M Fc-Lga6 Tray, Datasheet

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Signal Definitions
STPCLK# I STPCLK# (Stop Clock), when asserted, causes processors to enter a
low power Stop-Grant state. The processor issues a Stop-Grant
Acknowledge transaction, and stops providing internal clock signals
to all processor core units except the FSB and APIC units. The
processor continues to snoop bus transactions and service interrupts
while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
2
TCK I TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TDI I TDI (Test Data In) transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO O TDO (Test Data Out) transfers serial test data out of the processor.
TDO provides the serial output needed for JTAG specification support.
TESTHI[ 12:8 ] I TESTHI[12:8] must be connected to a V
TT
power source through a
resistor for proper processor operation. Refer to Section 2.6 for
TESTHI grouping restrictions.
THERMTRIP# O Assertion of THERMTRIP# (Thermal Trip) indicates the processor
junction temperature has reached a temperature beyond which
permanent silicon damage may occur. Measurement of the
temperature is accomplished through an internal thermal sensor.
Upon assertion of THERMTRIP#, the processor will shut off its internal
clocks (thus halting program execution) in an attempt to reduce the
processor junction temperature. To protect the processor its core
voltage (V
CC
) must be removed following the assertion of
THERMTRIP#. Intel also recommends the removal of V
TT
when
THERMTRIP# is asserted.
Driving of the THERMTRIP# signals is enabled within 10
μ s of the
assertion of PWRGOOD and is disabled on de-assertion of PWRGOOD.
Once activated, THERMTRIP# remains latched until PWRGOOD is de-
asserted. While the de-assertion of the PWRGOOD signal will de-
assert THERMTRIP#, if the processor’s junction temperature remains
at or above the trip level, THERMTRIP# will again be asserted within
10 μ s of the assertion of PWRGOOD.
1
TMS I TMS (Test Mode Select) is a JTAG specification support signal used by
debug tools.
See the Debug Port Design Guide for Intel
®
5000 Series Chipset
Memory Controller Hub (MCH) Systems (External Version) for further
information.
TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of all FSB agents.
TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
V
CCPLL
I The Dual-Core Intel® Xeon® Processor 5200 Series implements an
on-die PLL filter solution. The V
CCPLL
input is used as a PLL supply
voltage.
VCC_DIE_SENSE
VCC_DIE_SENSE2 O VCC_DIE_SENSE and VCC_DIE_SENSE2 provides an isolated, low
impedance connection to the processor core power and ground. This
signal should be connected to the voltage regulator feedback signal,
which insures the output voltage (that is, processor voltage) remains
within specification. Please see the applicable platform design guide
for implementation details.
VID[6:1] O VID[6:1] (Voltage ID) pins are used to support automatic selection of
power supply voltages (V
CC
). These are CMOS signals that are driven
by the processor and must be pulled up through a resistor.
Conversely, the voltage regulator output must be disabled prior to the
voltage supply for these pins becomes invalid. The VID pins are
needed to support processor voltage specification variations. See
Table 2-4 for definitions of these pins. The VR must supply the
voltage that is requested by these pins, or disable itself.
Table 5-1. Signal Definitions (Sheet 7 of 8)
Name Type Description Notes