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Specification Update

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Summary of Contents for DUAL-CORE - UPDATE REV 010

Page 1: ...Intel Pentium Dual Core Processor Specification Update December 2010 Revision 010...

Page 2: ...conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in thi...

Page 3: ...Specification Update 3 Contents Preface 5 Summary Tables of Changes 7 Identification Information 15 Errata 17 Specification Changes 55 Specification Clarifications 56 Documentation Changes 57...

Page 4: ...obile 965 Express Chipset Family Added M 0 stepping errata August 2007 316515 006 Added Processors based on the Intel Mobile 965 series chipset Added M 0 Errata and Microcode in separate tables Remove...

Page 5: ...heet 316519 Intel Pentium Dual Core Processor for Intel 965 Express Chipset Family Datasheet 318125 Related Documents Document Title Document Number Location Debug Port Design Guide for Crestline and...

Page 6: ...release of the specifications Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications...

Page 7: ...Changes as noted This table uses the following notations Codes Used in Summary Table Stepping X Erratum Specification Change or Clarification that applies to this stepping No mark or Blank Box This e...

Page 8: ...n processor with 800 MHz system bus 1 MB and 2 MB L2 cache versions T Mobile Intel Pentium 4 processor M U 64 bit Intel Xeon processor MP with up to 8 MB L3 cache V Mobile Intel Celeron processor on 1...

Page 9: ...for Intel Pentium Dual Core Mobile Processors Number D0 M0 Plans ERRATA AN1 X Fixed FST Instruction with Numeric and Null Segment Exceptions May Take Numeric Exception with Incorrect FPU Operand Point...

Page 10: ...elayed following a POPFD Instruction AN25 X Fixed Performance Monitoring Counters that Count External Bus Events May Report Incorrect Values after Processor Power State Transitions AN26 X X No Fix VER...

Page 11: ...Table LVT when an Interrupt is Pending May Cause an Unexpected Interrupt AN48 X X No Fix Using 2M 4M pages When A20M Is Asserted May Result in Incorrect Address Translations AN49 X Fixed Counter Enab...

Page 12: ...Performance Monitoring Event FP_ASSIST May Not be Accurate AN67 X X No Fix The BS Flag in DR6 May be Set for Non Single Step DB Exception AN68 X X No Fix BTM BTS Branch From Instruction Address May Be...

Page 13: ...ent Check Exception AN91 X No Fix PMI May Be Delayed to Next PEBS Event AN92 X No Fix An Asynchronous MCE during a Far Transfer May Corrupt ESP AN93 X No Fix B0 B3 Bits in DR6 May Not Be Properly Clea...

Page 14: ...h Cacheable and WC Memory Types May Lead to Memory Ordering Violations AN110 X No Fix RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Re...

Page 15: ...Table 1 Pentium Dual Core Mobile Processor on 65 nm Process Identification Information QDF S SPEC Processor Package Stepping CPUID FSB MHz Speed HFM LFM GHz Notes SL9VX T2060 Micro FCPGA D 0 06ECh 533...

Page 16: ...ion Information for 965 Express Chipset Family QDF S SPEC Processor Package Stepping CPUID FSB MHz Speed HFM LFM GHz Notes SLAEC T2310 Micro FCPGA M 0 06FDh 533 1 46 800 1 SLA4J T2370 Micro FCPGA M 0...

Page 17: ...not observed this erratum with any commercially available software or system Workaround The numeric exception handler should check the segment and if it is Null avoid further access to the data that c...

Page 18: ...a size of each write will now always be 8 bytes as opposed to the original data size and there may be a memory ordering violation WT there may be a memory ordering violation Workaround Software should...

Page 19: ...er than WC as specified in Intel 64 and IA 32 Architectures Software Developer s Manual Implication When this erratum occurs the memory page may be as UC rather than WC This may have a negative perfor...

Page 20: ...karound Operating system software should align GDT to 8 bytes as recommended in the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide For performance reas...

Page 21: ...ST m16int FIST m32int FISTP m16int FISTP m32int FISTP m64int Note that even if this combination of instructions is encountered there is also a dependency on the internal pipelining and execution state...

Page 22: ...ception will be generated instead of the expected general protection fault Workaround In general operating systems do not set the GD bit when they are in V86 mode The GD bit is generally set and used...

Page 23: ...inear addresses with different memory types Intel has strongly discouraged this practice as it may lead to undefined results Software that needs to implement memory aliasing should manage the memory t...

Page 24: ...removed AN22 Last Branch Records LBR Updates May Be Incorrect after a Task Switch Problem A Task State Segment TSS task switch may incorrectly set the LBR_FROM value to the LBR_TO value Implication Th...

Page 25: ...around for custom software is to execute at least one instruction following POPFD before issuing a JMP instruction Status For the steppings affected see the Summary Tables of Changes AN25 Performance...

Page 26: ...VERW VERR LSL LAR instructions Status For the steppings affected see the Summary Tables of Changes AN27 General Protection GP Fault May Not Be Signaled on Data Segment Limit Violation above 4 G Limit...

Page 27: ...ependent on the number of occurrences of the conditions described above while the counter is active Workaround None identified Status For the steppings affected see the Summary Tables of Changes AN30...

Page 28: ...terrupt Implication Data Breakpoints Single step operation on MOV SS POP SS instructions may be unreliable in the presence of SMI Workaround None Identified Status For the steppings affected see the S...

Page 29: ...ble DTS thermal interrupts by programming the thermal threshold and setting the respective thermal interrupt enable bit When programming DTS value the previous DTS threshold may be crossed This will g...

Page 30: ...mes May Appear to Have Not Occurred Problem With respect to the retirement of instructions stores to the uncacheable memory based APIC register space are handled in a non synchronized way For example...

Page 31: ...y an instruction that read from an I O port The SMM handler must not restart an I O instruction if the platform has not been configured to generate a synchronous SMI for the recorded I O port address...

Page 32: ...operating system use If this erratum occurs and the OS does not ensure that the processor never has a Null segment selector in the SS or CS segment registers the processor s behavior may become unpre...

Page 33: ...memory Status For the steppings affected see the Summary Tables of Changes AN49 Counter Enable bit 22 of IA32_CR_PerfEvtSel0 and IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon Architectural Performanc...

Page 34: ...VD MOVQ with MMX XMM register operands may issue a memory load before getting the DNA exception Workaround Code which performs loads from memory that has side effects can effectively workaround this b...

Page 35: ...unexpected processor behavior Implication This erratum may lead to livelock shutdown or other unexpected processor behavior Intel has not observed this erratum with any commercially available system...

Page 36: ...ed stores that span cache lines in the monitored address range Status For the steppings affected see the Summary Tables of Changes AN57 Writing Shared Unaligned Data that Crosses a Cache Line without...

Page 37: ...f WB and WT memory types may observe unpredictable behavior Intel chipset based platforms are not affected by this erratum Workaround None identified Intel does not support the use of WB and WT page m...

Page 38: ...gement mode the CPU will incorrectly update the LBR last branch record and the BTS branch trace store hence rendering their data invalid The corresponding data if sent out as a BTM on the system bus w...

Page 39: ...tual assist in the following specific cases FADD and FMUL instructions with a not a Number NaN operand and a memory operand FDIV instruction with zero operand value in memory In addition an assist eve...

Page 40: ...F Interrupt 16 DB is generated twice on the same instruction Workaround None identified Status For the steppings affected see the Summary Tables of Changes AN71 Fault on ENTER Instruction May Result i...

Page 41: ...r an access that results in either A or D bits being set in a Page table Entry PTE Implication Stale Translations may remain valid in TLB after a PTE update resulting in unpredictable system behavior...

Page 42: ...o an RSM inconsistency failure EFLAGS CR0 and CR4 may be incorrect In addition the EXF4 signal may still be asserted This may be observed if the processor is taken out of shutdown by NMI Implication A...

Page 43: ...ndent on the occurrences of the erratum condition while the counter is active Intel has not observed this erratum with any commercially available software Workaround None Identified Status For the ste...

Page 44: ...d see the Summary Tables of Changes AN85 EIP May Be Incorrect after Shutdown in IA 32e Mode Problem When the processor is going into shutdown state the upper 32 bits of the instruction pointer may be...

Page 45: ...sage mechanisms However during a specific boundary condition where the exception interrupt occurs right after the execution of an instruction at the lower canonical boundary 0x00007FFFFFFFFFFF in 64 b...

Page 46: ...ent the PEBS index is compared with the PEBS threshold and the index is incremented with every event If PEBS index is equal to the PEBS threshold a PMI Performance Monitoring Interrupt should be issue...

Page 47: ...ratum the processor may also count other types of instructions resulting in values higher than the number of actual retired SSE instructions Implication The event monitor instruction SIMD_INST_RETIRED...

Page 48: ...ee the Summary Tables of Changes AN98 Storage of PEBS Record Delayed Following Execution of MOV SS or STI Problem When a performance monitoring counter is configured for PEBS Precise Event Based Sampl...

Page 49: ...ception conditions is present following the code transition Code DB and code PF Code Segment Limit Violation GP and code PF Implication Software may observe either incorrect processing of code PF befo...

Page 50: ...o a WRMSR to one of the IA32_MTRR_PHYSMASKn MSRs with reserved bits set Implication When this erratum occurs a memory access may get an incorrect memory type leading to unexpected system operation As...

Page 51: ...tum by masking off bit 17 of the EAX register after coming out of reset Status For the steppings affected see the Summary Tables of Changes AN106 Instruction Fetch May Cause a Livelock during Snoops o...

Page 52: ...undefined results Software that needs to implement memory aliasing should manage the memory type consistency Status For the steppings affected see the Summary Tables of Changes AN108 A WB Store Follow...

Page 53: ...tion results Implication In the above sequence the processor may live lock or hang or RSM instruction may restart the interrupted processor context through a nondeterministic EIP offset in the code se...

Page 54: ...nstruction result may be incorrect Implication A register IP relative instruction result may be incorrect and could cause software to read from or write to an incorrect memory location This may result...

Page 55: ...Specification Changes Specification Update 55 Specification Changes There are no specification changes in this specification update revision...

Page 56: ...Specification Clarifications 56 Specification Update Specification Clarifications There are no specification clarifications in this specification update revision...

Page 57: ...tion changes in this specification update revision Documentation changes for the Intel 64 and IA 32 Architectures Software Developer s Manual Volumes 1 2A 2B 3A and 3B will be posted in a separate doc...

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