Errata
18
Specification Update
AN3.
Erratum removed
AN4.
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types May Use an
Incorrect Data Size or Lead to Memory-Ordering Violations
Problem:
Under certain conditions as described in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 3A: System Programming Guide, the processor
performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP
MOVS/REP STOS instructions that cross page boundaries from WB/WC memory types
to UC/WP/WT memory types, may start using an incorrect data size or may observe
memory ordering violations.
Implication:
Upon crossing the page boundary the following may occur, dependent on the new
page memory type:
•
UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
•
WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
•
WT there may be a memory ordering violation.
Workaround:
Software should avoid crossing page boundaries from WB or WC memory type to UC,
WP or WT memory type within a single REP MOVS or REP STOS instruction that will
execute with fast strings enabled.
Status:
For the steppings affected, see the
AN5.
Memory Aliasing with Inconsistent A and D Bits May Cause Processor
Deadlock
Problem:
In the event that software implements memory aliasing by having two Page Directory
Entries (PDEs) point to a common Page Table Entry (PTE) and the Accessed and Dirty
bits for the two PDEs are allowed to become inconsistent the processor may become
deadlocked.
Implication:
This erratum has not been observed with commercially available software.
Workaround:
Software that needs to implement memory aliasing in this way should manage the
consistency of the Accessed and Dirty bits.
Status:
