Errata
46
Specification Update
AN90.
IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
Problem:
In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET
instruction even though alignment checks were disabled at the start of the IRET. This
can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs
from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the
stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e
mode, RSP is aligned to a 16-byte boundary before pushing the stack frame.
Implication:
In IA-32e mode, under the conditions given above, an IRET can get a #AC even if
alignment checks are disabled at the start of the IRET. This erratum can only be
observed with a software generated stack frame.
Workaround:
Software should not generate misaligned stack frames for use with IRET.
Status:
For the steppings affected, see the
AN91.
PMI May Be Delayed to Next PEBS Event
Problem:
After a PEBS (Precise Event-Based Sampling) event, the PEBS index is compared with
the PEBS threshold, and the index is incremented with every event. If PEBS index is
equal to the PEBS threshold, a PMI (Performance Monitoring Interrupt) should be
issued. Due to this erratum, the PMI may be delayed by one PEBS event.
Implication:
Debug Store Interrupt Service Routines may observe delay of PMI occurrence by one
PEBS event.
Workaround:
None identified.
Status:
For the steppings affected, see the
AN92.
An Asynchronous MCE during a Far Transfer May Corrupt ESP
Problem:
If an asynchronous machine check occurs during an interrupt, call through gate, FAR
RET or IRET and in the presence of certain internal conditions, ESP may be corrupted.
Implication:
If the MCE (Machine Check Exception) handler is called without a stack switch, then a
triple fault will occur due to the corrupted stack pointer, resulting in a processor
shutdown. If the MCE is called with a stack switch, for example when the CPL (Current
Privilege Level) was changed or when going through an interrupt task gate, then the
corrupted ESP will be saved on the stack or in the TSS (Task State Segment), and will
not be used.
Workaround:
Use an interrupt task gate for the machine check handler.
Status:
