Errata
36
Specification Update
AN55.
Erratum removed
AN56.
Split Locked Stores May Not Trigger the Monitoring Hardware
Problem:
Logical processors normally resume program execution following the MWAIT, when
another logical processor performs a write access to a WB cacheable address within
the address range used to perform the MONITOR operation. Due to this erratum, a
logical processor may not resume execution until the next targeted interrupt event or
O/S timer tick following a locked store that spans across cache lines within the
monitored address range.
Implication:
The logical processor that executed the MWAIT instruction may not resume execution
until the next targeted interrupt event or O/S timer tick in the case where the
monitored address is written by a locked store which is split across cache lines.
Workaround:
Do not use locked stores that span cache lines in the monitored address range.
Status:
For the steppings affected, see the
AN57.
Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering Issue
Problem:
Software which is written so that multiple agents can modify the same shared
unaligned memory location at the same time may experience a memory ordering
issue if multiple loads access this shared data shortly thereafter. Exposure to this
problem requires the use of a data write which spans a cache line boundary.
Implication:
This erratum may cause loads to be observed out of order. Intel has not observed this
erratum with any commercially available software or system.
Workaround:
Software should ensure at least one of the following is true when modifying shared
data by multiple agents:
•
The shared data is aligned
•
Proper semaphores or barriers are used in order to prevent concurrent data
accesses
Status:
