Errata
20
Specification Update
AN9.
LTR Instruction May Result in Unexpected Behavior
Problem:
Under certain circumstances an LTR (Load Task Register) instruction may result in an
unexpected behavior if all the following conditions are met:
1.
Invalid data selector of the TR (Task Register) resulting with either #GP (General
Protection Fault) or #NP (Segment Not Present Fault).
2.
GDT (Global Descriptor Table) is not 8-bytes aligned.
Implication:
If all conditions have been met then under certain circumstances LTR instruction may
result in system hang, memory corruption or other unexpected behavior. This
erratum has not been observed in commercial operating systems or software.
Workaround:
Operating system software should align GDT to 8-bytes, as recommended in the
Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System
Programming Guide. For performance reasons, GDT is typically aligned to 8-bytes.
Status:
For the steppings affected, see the
AN10.
Invalid Entries In Page-Directory-Pointer-Table Register (PDPTR)
May Cause General Protection (#GP) Exception If the Reserved Bits
Are Set to One
Problem:
Invalid entries in the Page-Directory-Pointer-Table Register (PDPTR) that have the
reserved bits set to one may cause a General Protection (#GP) exception.
Implication:
Intel has not observed this erratum with any commercially available software.
Workaround:
Do not set the reserved bits to one when PDPTR entries are invalid.
Status:
For the steppings affected, see the
AN11.
Erratum removed
