Errata
38
Specification Update
AN61.
Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
Problem:
A partial memory state save of the 512-byte FXSAVE image or a partial memory state
restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit
while the processor is operating in 16-bit mode or if a memory address exceeds the
4GB limit while the processor is operating in 32-bit mode.
Implication:
FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as expected
but the memory state may be only partially saved or restored.
Workaround:
Software should avoid memory accesses that wrap around the respective 16-bit and
32-bit mode memory limits.
Status:
For the steppings affected, see the
AN62.
Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM
Problem:
After a return from SMM (system management mode), the CPU will incorrectly update
the LBR (last branch record) and the BTS (branch trace store), hence rendering their
data invalid. The corresponding data if sent out as a BTM on the system bus will also
be incorrect. Note: This issue would only occur when one of the 3 above mentioned
debug support facilities are used.
Implication:
The value of the LBR, BTS, and BTM immediately after an RSM operation should not
be used.
Workaround:
None identified.
Status:
For the steppings affected, see the
AN63.
Erratum removed.
AN64.
Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
Unpredictable System Behavior
Problem:
Returning back from SMM mode into real mode while EFLAGS.VM is set in SMRAM may
result in unpredictable system behavior.
Implication:
If SMM software changes the values of the EFLAGS.VM in SMRAM, it may result in
unpredictable system behavior. Intel has not observed this behavior in commercially
available software.
Workaround:
SMM software should not change the value of EFLAGS.VM in SMRAM.
Status:
For the steppings affected, see the
