Errata
Specification Update
47
AN93.
B0-B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint
Problem:
B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly
cleared when the following sequence happens:
1.
POP instruction to SS (Stack Segment) selector.
2.
Next instruction is FP (Floating Point) that gets FP assist followed by code
breakpoint.
Implication:
B0-B3 bits in DR6 may not be properly cleared.
Workaround:
None identified.
Status:
For the steppings affected, see the
AN94.
Performance Monitor SSE Retired Instructions May Return Incorrect
Values
Problem:
The SIMD_INST_RETIRED (Event: C7H) is used to track retired SSE instructions. Due
to this erratum, the processor may also count other types of instructions resulting in
values higher than the number of actual retired SSE instructions.
Implication:
The event monitor instruction SIMD_INST_RETIRED may report count higher than
expected.
Workaround:
None identified.
Status:
For the steppings affected, see the
AN95.
Performance Monitoring Events for L1 and L2 Miss May Not Be
Accurate
Problem:
Performance monitoring events 0CBh with an event mask value of 02h or 08h
(MEM_LOAD_RETIRED.L1_LINE_MISS or MEM_LOAD_RETIRED.L2_LINE_MISS) may
under count the cache miss events.
Implication:
These performance monitoring events may show a count which is lower than
expected; the amount by which the count is lower is dependent on other conditions
occurring on the same load that missed the cache.
Workaround:
None Identified.
Status:
