Errata
52
Specification Update
AN107.
Use of Memory Aliasing with Inconsistent Memory Type May Cause a
System Hang or a Machine Check Exception
Problem:
Software that implements memory aliasing by having more than one linear addresses
mapped to the same physical page with different cache types may cause the system
to hang or to report a machine check exception (MCE). This would occur if one of the
addresses is non-cacheable and used in a code segment and the other is a cacheable
address. If the cacheable address finds its way into the instruction cache, and the
non-cacheable address is fetched in the IFU, the processor may invalidate the non-
cacheable address from the fetch unit. Any micro-architectural event that causes
instruction restart will be expecting this instruction to still be in the fetch unit and lack
of it will cause a system hang or an MCE.
Implication:
This erratum has not been observed with commercially available software.
Workaround:
Although it is possible to have a single physical page mapped by two different linear
addresses with different memory types, Intel has strongly discouraged this practice as
it may lead to undefined results. Software that needs to implement memory aliasing
should manage the memory type consistency
Status:
For the steppings affected, see the
AN108.
A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
Problem:
Under certain conditions, as described in the Software Developers Manual section
"Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family
Processors", the processor may perform REP MOVS or REP STOS as write combining
stores (referred to as “fast strings”) for optimal performance. FXSAVE may also be
internally implemented using write combining stores. Due to this erratum, stores of a
WB (write back) memory type to a cache line previously written by a preceding fast
string/FXSAVE instruction may be observed before string/FXSAVE stores.
Implication:
A write-back store may be observed before a previous string or FXSAVE related store.
Intel has not observed this erratum with any commercially available software.
Workaround:
Software desiring strict ordering of string/FXSAVE operations relative to subsequent
write-back stores should add an MFENCE or SFENCE instruction between the
string/FXSAVE operation and following store-order sensitive code such as that used for
synchronization.
Status:
