Errata
Specification Update
33
AN48.
Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect
Address Translations
Problem:
An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero)
to emulates real-address mode address wraparound at 1 megabyte. However, if all of
the following conditions are met, address bit 20 may not be masked.
•
paging is enabled
•
a linear address has bit 20 set
•
the address references a large page
•
A20M# is enabled
Implication:
When A20M# is enabled and an address references a large page the resulting
translated physical address may be incorrect. This erratum has not been observed
with any commercially available operating system.
Workaround:
Operating systems should not allow A20M# to be enabled if the masking of address
bit 20 could be applied to an address that references a large page. A20M# is normally
only used with the first megabyte of memory.
Status:
For the steppings affected, see the
AN49.
Counter Enable bit [22] of IA32_CR_PerfEvtSel0 and
IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon (Architectural
Performance Monitoring) Specification
Problem:
According to the Architectural Performance Monitoring specification the two PerfMon
counters can be disabled/enabled through the corresponding Counter Enable bit [22]
of IA32_CR_PerfEvtSel0/1.
Due to this erratum the following occurs:
1.
bit [22] of IA32_CR_PerfEvtSel0 enables/disables both counters
2.
bit [22] of IA32_CR_PerfEvtSel1 doesn't function
Implication:
Software cannot enable/disable only one of the two PerfMon counters through the
corresponding Counter Enable bit [22] of IA32_CR_PerfEvtSel0/1.
Workaround:
Software should enable/disable both PerfMon counters together through Counter
Enable bit [22] of IA32_CR_PerfEvtSel0 only. Alternatively, Software can effectively
disable any one of the counters by clearing both Kernel and App bits [17:16] in the
corresponding IA32_CR_PerfEvtSel0/1.
Status:
