Errata
24
Specification Update
AN18.
Erratum removed
AN19.
Erratum removed
AN20.
LOCK# Asserted during a Special Cycle Shutdown Transaction May
Unexpectedly Deassert
Problem:
During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is
received during a snoop phase and the Locked transaction is pipelined on the front
side bus (FSB), LOCK# may unexpectedly deassert.
Implication:
When this erratum occurs, the system may hang during shutdown. Intel has not
observed this erratum with any commercially available systems or software.
Workaround:
None identified.
Status:
For the steppings affected, see the
AN21.
Erratum removed.
AN22.
Last Branch Records (LBR) Updates May Be Incorrect after a Task
Switch
Problem:
A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM value to
the LBR_TO value.
Implication:
The LBR_FROM will have the incorrect address of the Branch Instruction.
Workaround:
None identified.
Status:
For the steppings affected, see the
AN23.
Address Reported By Machine-Check Architecture (MCA) on Single-bit
L2 ECC Errors May Be Incorrect
Problem:
When correctable single-bit ECC errors occur in the L2 cache the address is logged in
the MCA address register (MCi_ADDR). Under some scenarios, the address reported
may be incorrect.
Implication:
Software should not rely on the value reported in MCi_ADDR, for Single-bit L2 ECC
errors
Workaround:
None identified.
Status:
