Errata
Specification Update
37
AN58.
MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
Problem:
When an MCE occurs during execution of a RDMSR instruction for MSRs Actual
Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock Count
(IA32_MPERF), the current and subsequent RDMSR instructions for these MSRs may
contain incorrect data.
Implication:
After an MCE event, accesses to the IA32_APERF and IA32_MPERF MSRs may return
incorrect data. A subsequent reset will clear this condition.
Workaround:
None identified.
Status:
For the steppings affected, see the
AN59.
Using Memory Type Aliasing with Memory Types WB/WT May Lead to
Unpredictable Behavior
Problem:
Memory type aliasing occurs when a single physical page is mapped to two or more
different linear addresses, each with different memory type. Memory type aliasing
with the memory types WB and WT may cause the processor to perform incorrect
operations leading to unpredictable behavior.
Implication:
Software that uses aliasing of WB and WT memory types may observe unpredictable
behavior. Intel chipset-based platforms are not affected by this erratum.
Workaround:
None identified. Intel does not support the use of WB and WT page memory type
aliasing.
Status:
For the steppings affected, see the
AN60.
Code Breakpoint May be Taken after POP SS Instruction If It Is
followed by an Instruction That Faults
Problem:
A POP SS instruction should inhibit all interrupts including Code Breakpoints until after
execution of the following instruction. This allows sequential execution of POP SS and
MOV eSP, eBP instructions without having an invalid stack during interrupt handling.
However, a code breakpoint may be taken after POP SS if it is followed by an
instruction that faults, this results in a code breakpoint being reported on an
unexpected instruction boundary since both instructions should be atomic.
Implication:
This can result in a mismatched Stack Segment and SP. Intel has not observed this
erratum with any commercially available software, or system.
Workaround:
As recommended in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, the use "POP SS" in conjunction with "MOV eSP, eBP" will avoid the failure
since the "MOV" will not fault.
Status:
