Intel DUAL-CORE - UPDATE REV 010, Specification

Page: 13 / 57

Summary Tables of Changes
Specification Update 13
Number D0 M0 Plans ERRATA
AN81 X X No Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
AN82
X
No Fix Count Value for Performance-Monitoring Counter PMH_PAGE_WALK
May Be Incorrect
AN83 No Fix Erratum Removed
AN84
X
No Fix Some Bus Performance Monitoring Events May Not Count Local
Events under Certain Conditions
AN85 X No Fix EIP May Be Incorrect after Shutdown in IA-32e Mode
AN86
X
No Fix Upper 32 bits of ‘From’ Address Reported through BTMs or BTSs
May Be Incorrect
AN87
X
No Fix Code Segment Limit/Canonical Faults on RSM May be Serviced
before Higher Priority Interrupts/Exceptions
AN88
X
No Fix LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
AN89
X
No Fix CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or
Equal to 2
48
May Terminate Early
AN90
X
No Fix IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
AN91 X No Fix PMI May Be Delayed to Next PEBS Event
AN92 X No Fix An Asynchronous MCE during a Far Transfer May Corrupt ESP
AN93
X
No Fix B0-B3 Bits in DR6 May Not Be Properly Cleared after Code
Breakpoint
AN94
X
No Fix Performance Monitor SSE Retired Instructions May Return Incorrect
Values
AN95
X
No Fix Performance Monitoring Events for L1 and L2 Miss May Not Be
Accurate
AN96 No Fix Erratum Removed
AN97
X
No Fix
Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is
Counted Incorrectly for PMULUDQ Instruction
AN98
X
No Fix
Storage of PEBS Record Delayed Following Execution of MOV SS or
STI
AN99
X
No Fix Updating Code Page Directory Attributes without TLB Invalidation
May Result in Improper Handling of Code #PF
AN100
X
No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over
Count
AN101
X
No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May
Prevent Triggering of the Monitoring Hardware
AN102
X
No Fix A Memory Access May Get a Wrong Memory Type Following a #GP
due to WRMSR to an MTRR Mask
AN103
X
No Fix PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR
Information
AN104 No Fix Erratum Removed