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Intel® 460GX Chipset Software Developer’s Manual

6-25

Data Integrity and Error Handling

•

PCI Outbound Write Que Data Parity Error - This error signifies that either a) data was
received from the Expander bus with bad parity or b) the OB write Que was corrupted. As data
is read from the queue and passed to the PCI bus, the parity is checked.

•

AGP Low-priority Read Data Que Parity Error - This error signifies that either a) data was
received from the Expander bus with bad parity or b) the read Que was corrupted. As data is
read from the queue and passed to the AGP bus, the parity is checked.

•

AGP Hi-priority Read Data Que Parity Error - This error signifies that either a) data was
received from the Expander bus with bad parity or b) the read Que was corrupted. As data is
read from the queue and passed to the AGP bus, the parity is checked.

•

PCI Inbound Read Que Data Parity Error - This error signifies that either a) data was received
from the Expander bus with bad parity or b) the read Que was corrupted. As data is read from
the queue and passed to the AGP bus, the parity is checked. This is for PCI reads done by the
graphics card. The parity on the PCI data will be poisoned out to the card as the data is
returned.

6.11.4.3

Multiple Errors

In the case that 2 or more errors occur at the same cycle, multiple bits are set in the FERR register.
This should be an extremely rare case. Software can read the register and check that only one bit is
set. The data that is captured along with the error is indeterminate. Since there are multiple
registers for error data, 2 errors may cause the Expander and PCI error registers to have valid data.
Or, if there were 2 errors from Expander bus at the same time, then the Expander data-error register
may have been set by either error.

Figure 6-3. GXB Error Flow

AGP Bus

SAC

IB

SAC

UpS

Data

SAC

DnS

Data

CFG
Ctrl

SAC

OB

SRAM

SAC Interconnect

Check Parity.
If PCI, then corrupt outgoing parity.

Generate parity
in Expander format,
data and BE. If

Check parity.

On HDR: BINIT#. Drop
PKT and data. Set FERR.

PCI data is bad,
poison into
buffer.

Chk parity.

Place data into buffer
with parity as received from
Expander (16 data, 2 BE, 1 par.)

Pass data to SAC with
parity from queue, don’t
check outgoing parity.

GART

AGP
High
Read
Data

AGP
Low
Read
Data

PCI
IB
Read
Data

PCI
OB
Write
Data

AGP
High
Write
Data

AGP
Low
Write
Data

PCI
IB
Write
Data

PCI
OB
Read
Data

PCI
OB

PCI
IB

AGP
LO

AGP
HI

PCI
IB

AGP
Low

AGP
High

AGP
Que

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Summary of Contents for 460GX

Page 1: ...Intel 460GX Chipset System Software Developer s Manual June 2001 Document Number 248704 001 ...

Page 2: ...y make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel 460GX chipset may contain de...

Page 3: ... 2 2 Access Restrictions 2 2 2 2 1 Partitioning 2 2 2 2 2 Register Attributes 2 3 2 2 3 Reserved Bits Defined in Registers 2 3 2 2 4 Reserved or Undefined Register Locations 2 3 2 2 5 Default Upon Reset 2 3 2 2 6 Consistency 2 4 2 2 7 GART Programming Region 2 4 2 3 I O Mapped Registers 2 4 2 3 1 CONFIG_ADDRESS Configuration Address Register 2 4 2 3 2 CONFIG_DATA Configuration Data Register 2 5 2 ...

Page 4: ... 1 4 1 Memory Map 4 1 4 1 1 Compatibility Region 4 1 4 1 2 Low Extended Memory Region 4 3 4 1 3 Medium Extended Memory Region 4 3 4 1 4 High Extended Memory above 4G 4 4 4 1 5 Re mapped Memory Areas 4 4 4 2 I O Address Map 4 5 4 3 Devices View of the System Memory Map 4 7 4 4 Legal and Illegal Address Disposition 4 8 5 Memory Subsystem 5 1 5 1 Organization 5 1 5 1 1 DIMM Types 5 3 5 2 Interleaving...

Page 5: ... 6 11 6 8 Multiple Errors 6 11 6 8 1 SDC Multiple Errors 6 12 6 8 2 SAC Multiple Errors 6 13 6 8 3 Single Errors with Multiple Reporting 6 13 6 8 4 Error Anomalies 6 13 6 9 Data Flow Errors 6 14 6 10 Error Conditions 6 15 6 10 1 Table of Errors 6 15 6 11 PCI Integrity 6 20 6 11 1 PCI Bus Monitoring 6 20 6 11 2 PXB as Master 6 20 6 11 3 PXB as Target 6 21 6 11 4 GXB Error Flow 6 22 6 12 WXB Data In...

Page 6: ...LT Master Latency Timer Register 8 6 8 1 10 HDR Header Register 8 6 8 1 11 Base Address 8 7 8 1 12 SVID Subsystem Vendor Identification 8 7 8 1 13 SID Subsystem ID 8 7 8 1 14 Interrupt Line 8 7 8 1 15 Interrupt Pin 8 8 8 1 16 Hot Plug Slot Identifier 8 8 8 1 17 Miscellaneous Hot Plug Configuration 8 8 8 1 18 Hot Plug Features 8 9 8 1 19 Switch Change SERR Status 8 9 8 1 20 Power Fault SERR Status ...

Page 7: ... DMA Single Word DMA Non ultra DMA Capability 10 5 10 5 6 IFB Timing Settings 10 9 10 5 7 Drive Configuration for Selected Timings 10 11 10 5 8 Settings Checklist 10 13 10 5 9 Example Configurations 10 14 10 5 10 Ultra DMA System Software Considerations 10 16 10 5 11 Additional Ultra DMA PCI Bus Master IDE Device Driver Considerations 10 17 10 6 USB Resume Enable Bit 10 19 11 LPC FWH Interface Con...

Page 8: ...2 IDE Controller Register Descriptions PCI Function 1 12 1 12 2 1 VID Vendor Identification Register Function 1 12 2 12 2 2 DID Device Identification Register Function 1 12 2 12 2 3 PCICMD PCI Command Register Function 1 12 2 12 2 4 PCISTS PCI Device Status Register Function 1 12 3 12 2 5 CLASSC Class Code Register Function 1 12 3 12 2 6 MLT Master Latency Timer Register Function 1 12 4 12 2 7 BMI...

Page 9: ... Configuration Registers Function 3 14 1 14 2 System Management Register Descriptions 14 2 14 2 1 VID Vendor Identification Register Function 3 14 2 14 2 2 DID Device Identification Register Function 3 14 2 14 2 3 PCICMD PCI Command Register Function 3 14 2 14 2 4 PCISTS PCI Device Status Register Function 3 14 3 14 2 5 RID Revision Identification Register Function 3 14 3 14 2 6 CLASSC Class Code ...

Page 10: ... RTC Interrupts 15 17 15 5 4 Lockable RAM Ranges 15 17 16 IFB Power Management 16 1 16 1 Overview 16 1 16 2 IFB Power Planes 16 2 16 2 1 Power Plane Descriptions 16 2 16 2 2 SMI Generation 16 2 16 2 3 SCI Generation 16 3 16 2 4 Sleep States 16 3 16 2 5 ACPI Bits Not Implemented by IFB 16 4 16 2 6 Entry Exit for the S4 and S5 States 16 4 16 3 Handling of Power Failures in IFB 16 5 Figures 1 1 Diagr...

Page 11: ...ead Matching Criteria 7 11 7 3 Burst Write Combining Modes 7 13 7 4 Burst Write Combining Examples with 3 Writes in 1X Transfer Mode 7 13 7 5 Bandwidth Estimates for Various Request Sizes 7 14 8 1 IHPC Configuration Register Space 8 2 8 2 IHPC Memor Mapped Register Space 8 11 9 1 PCI Configuration Registers Function 0 PCI to LPC FWH Interface Bridge 9 1 9 2 PCI Configuration Registers Function 1 I...

Page 12: ...CI Configuration Registers Function 1 IDE Interface 12 1 12 2 Ultra DMA 33 Timing Mode Settings 12 9 12 3 DMA PIO Timing Values Based on IFB Cable Mode and System Speed 12 9 12 4 Interrupt Activity Status Combinations 12 11 13 1 PCI Configuration Registers Function 2 13 1 13 2 Run Stop Debug Bit Interaction 13 9 15 1 SERIRQ Frames 15 9 15 2 RTC Standard RAM Bank 15 14 16 1 IFB Power States and Con...

Page 13: ...mory controller interface and appropriate bridges to PCI AGP 4X and other standard I O buses Figure 1 1 illustrates the basic system configuration of a four processor platform Figure 1 1 Diagram of a Typical Intel 460GX Chipset based System with AGP 000346e U S B GXB G raphics E xp ansion B ridge Expander Buses PXB PC I E xpan sion Brid ge A G P 4XM ode S lot G AR T S R A M C om patib ility P C I ...

Page 14: ...2466GX Wide and fast PCI Expander Bridge Provides the primary control and data interface for two independent 64 bit 66 MHz PCI interfaces This device attaches to the SAC via an Expander bus PXB 82467GX PCI Expander Bridge Provides the primary control and data interface for two independent 32 bit 33 MHz PCI interfaces These two 32 bit interfaces may operate together to produce a single 64 bit 33 MH...

Page 15: ...ess and data flows protected by parity throughout chipset ECC bits in DRAM accessible by diagnostics Fault recording of multiple errors sticky through reset JTAG TAP port for debug and boundary scan capability I2C slave interface for viewing and modifying specific error and configuration registers Bus memory and I O performance counters Support of ACPI DMI functions support is provided in the IFB ...

Page 16: ...ing 533 MB s peak bandwidth Each Expander bus supports a single PXB or WXB Two Expander busses can be configured to support a GXB Full support for the PCI Configuration Space Enable CSE protocol to devices on all Expander ports Data streaming support between Expanders and DRAM up to 533 MB s per Expander port All outbound memory and I O reads except locked reads are deferred All outbound memory sp...

Page 17: ...s operation supports Universal and 3 3 Volt PCI cards PCI Specification Revision 2 2 Integrated Hot Plug controller 1 5 3 GXB Features The GXB is AGP and AGP 4X mode compatible nominal 66 MHz 266 MHz 1 GB s peak bandwidth The GXB supports pipelined operation or sideband signals on AGP 4X mode bus AGP address space of 1 GB or 256 MB supported Also supports 32 GB of GART window if 4 MB pages are use...

Page 18: ...at least one PID located on the compatibility PCI bus The compatibility PID will handshake with the IFB before delivering a south bridge compatibility device interrupt The same PID may also be used to deliver some portion of the PCI based interrupts The system implementor can choose how many PIDs are used in the platform If enough interrupt lines are shared there need be only one PID in the system...

Page 19: ... Universal Serial Bus Specification http www usb org System Management Bus Specification Rev 1 0 Low Pin Count LPC Interface Specification Rev 1 0 Note Contact your Intel representative for the latest revision of the documents without document numbers 1 9 Revision History Date Description June 2001 Initial release ...

Page 20: ...Introduction 1 8 Intel 460GX Chipset Software Developer s Manual ...

Page 21: ...egisters status and error registers This chapter describes how the configuration spaces are accessed then provides detailed descriptions of each register 2 1 Access Mechanism The PCI specification defines two bus cycles to access PCI configuration space Configuration Read and Configuration Write While memory and I O spaces are supported by the microprocessor configuration space is not directly sup...

Page 22: ...f the registers are shared between the spaces that is the SAC and each PCI bus in the PXB have separate control and status registers Configuration registers are accessed using an address comprised of the PCI Bus Number the Device Number within the bus and the Register Number within the Device Accesses to devices on Bus 0 and Bus CBN are serviced by the 460GX chipset depending on their device numbe...

Page 23: ...tract the defined bits and not rely on reserved bits being any particular value On writes software must ensure that the values of reserved bit positions are preserved That is the values of reserved bit positions must first be read merged with the new values for other bit positions and then written back Note the software does not need to perform read merge write operation for the CONFIG_ADDRESS reg...

Page 24: ... configuration space and determines what portion of configuration space is visible through the Configuration Data window The following sections define the fields within the CONFIG_ADDRESS and CONFIG_DATA registers The 460GX chipset s device ID mapping into the CONFIG_ADDRESS definition is shown in Table 2 1 2 3 1 CONFIG_ADDRESS Configuration Address Register I O Address CF8h Dword Size 32 bits Def...

Page 25: ...s field is mapped to AD 7 2 during PCI configuration cycles 1 0 reserved 0 2 3 2 CONFIG_DATA Configuration Data Register I O Address CFCh Size 32 bits Default Value 00000000h Attribute Read Write Sticky No Locked No CONFIG_DATA is a 32 bit read write window into configuration space The portion of configuration space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS ...

Page 26: ...t the DED bit is sent from the SDC to the SAC on a Retire ITID command Bits Description 7 Disable This bit can be written by software When set the ITID is retired immediately and not captured Therefore there can be no checking of the address See Section 6 for the usage of this bit 6 Valid If set then the ITID in bits 5 0 is valid and shows the address of a double bit memory error Writing a 1 to th...

Page 27: ...e Command Underflow card A Stack R SCAR 26 Store Write Command Underflow card B Stack L SCBL 25 Store Write Command Underflow card B Stack R SCBR One of these 4 is asserted when a signal is sent from the SDC to the SAC indicating write data was sent to the MDC and there is no outstanding write in the SAC 24 SDC Correctable Memory Error SCME Reports correctable DRAM errors single bit ECC errors Thi...

Page 28: ...s is above TOM and not inside the I O gap below 4 GB 11 Illegal HITM IHS HITM on non memory access 10 Unsupported ASZ 1 0 ASE Processor access to an address above 64 GB so that ASZ 10b or 11b 9 System Bus Address Parity Error AE Parity error on A 36 3 8 System Bus Request Parity Error RQE Parity error on REQ 4 0 7 PDB ITID Parity Error IPE Parity error on the ITID bus from SDC to SAC 6 Retirement ...

Page 29: ...96 64 A 35 3 b phase 63 43 Reserved 0 42 LOCK a phase 41 ADS a phase 40 RP for REQa Parity on REQa signals 39 35 REQa REQa signals on error 34 33 AP 1 0 a phase Address parity for failing address 32 0 Aa 35 3 a phase System Bus System Address of Error 2 4 1 7 BIUITID BIU ITID Register Bus CBN Device Number 00h Function 1 Address Offset 80h Size 8 bits Default Value 0 Attribute Read Write Sticky No...

Page 30: ...the first occurrence of an OB lock sequence 46 43 Dst The destination of the transaction 42 ORetry A retry due to HITO 41 36 CMD The command for the transaction 35 P2P Set for peer to peer transactions 34 FEorR The end of request bit from the Expander port 33 30 FRoute The Expander bus route 29 22 FLEN The length on the Expander bus 21 12 FTID The Expander id 11 9 Len The length of the transaction...

Page 31: ...umber 04h Address Offset 48h Size 8 bits Default Value 00h Attribute Read Only New Value Latched anytime appropriate FERR register bit is set This register records and latches the ECC checkbits corresponding to the first SEC detected by memory interface 0 in the SDC Bits Description 7 0 ECC ECC of Error 2 4 2 3 SEC0_TXINFO_FERR TXINFO on First Memory Card B SEC Bus CBN Device Number 04h Address Of...

Page 32: ...riate FERR register bit is set This register records and latches the ECC checkbits corresponding to the first SEC detected by memory interface 0 in the SDC Bits Description 7 0 ECC ECC of Error 2 4 2 6 DED0_TXINFO_FERR TXINFO on First Memory Card B DED Bus CBN Device Number 04h Address Offset 59 5Ah Size 16 bits Default Value 00h Attribute Read Only New Value Latched anytime appropriate FERR regis...

Page 33: ...Error 2 4 2 9 SEC1_TXINFO_FERR TXINFO on First Memory Card A SEC Bus CBN Device Number 04h Address Offset 69 6Ah Size 16 bits Default Value 00h Attribute Read Only New Value Latched anytime appropriate FERR register bit is set This register records the ITID and failing chunk corresponding to the first SEC detected by memory interface 1 in the SDC Bits Description 15 9 reserved 0 8 6 DC Data Chunk ...

Page 34: ...e SDC Bits Description 15 9 reserved 0 8 6 DC Data Chunk of ITID 5 0 ITID ITID of error 2 4 2 13 SDC_FERR First Error Status Register Bus CBN Device Number 04h Address Offset 80 83h Size 32 bits Default Value 0000h Attribute Read Write to Clear This register records the first error condition detected in the SDC Writing a 1 to this register will clear the bit in both SDC_FERR and the same bit in SD...

Page 35: ...ss 17 Load Overlapping Forward Card B WrRd0 Memory interface 1 detected simultaneous read and write operation Write and Read collision 16 Forward Overlapping Load Card B RdWr0 Memory interface 1 detected simultaneous read and write operation Read and write collision 15 Forward Underflow Card B Right Stack Error FR0 Memory interface 0 received Forward right Bank without corresponding Store command ...

Page 36: ...within the SDC Writing a 1 to this register will clear the bit in both SDC_NERR and the same bit in SDC_FERR Bits Description 31 0 See SDC_FERR for bit definitions 2 4 2 15 PCMD_FERR Command on First PCMD Parity Error Bus CBN Device Number 04h Address Offset 88 8Bh Size 32 bits Default Value 00h Attribute Read Only New Value Latched anytime appropriate FERR register bit is set This register record...

Page 37: ...alf of double pumped transfer 3 0 Response Bus for 1st half of double pumped transfer 2 4 2 18 DPBRLE_FERR Private Data Bus Receive Length Error Bus CBN Device Number 04h Address Offset 8Eh Size 8 bits Default Value 0h Attribute Read Only New Value Latched anytime appropriate FERR register bit is set This register indicates that the amount of data transferred from the SAC to the SDC for a given tr...

Page 38: ...Ah Size 8 bits Default Value 00h Attribute Read Write This register is used to test the ECC error detection logic of the host processor bus To test this register is written with a masking function All subsequent processor reads will received a masked version of ECC code To disable testing the mask value is left at 0h the default The mask is a bit wise XOR with the computed ECC Bits Description 7 0...

Page 39: ...RR Parity on First PVD Parity Error Bus CBN Device Number 04h Address Offset D8h Size 8 bits Default Value 0 Attribute Read Only New Value Latched anytime appropriate FERR register bit is set This register records and latches the data associated with the first parity error detected on the PVD bus Bits Description 7 4 reserved 0 3 0 Double byte parity of error 2 4 2 25 PVD_TXINFO_FERR TXINFO on Fir...

Page 40: ...iate FERR register bit is set This register records and latches the ECC checkbits corresponding to the first SEC detected by system bus interface in the SDC Bits Description 7 0 ECC ECC of Error 2 4 2 28 SECF_TXINFO_FERR TXINFO on First System Bus SEC Bus CBN Device Number 04h Address Offset E9 EAh Size 16 bits Default Value 00h Attribute Read Only New Value Latched anytime appropriate FERR regist...

Page 41: ... ECC ECC of Error 2 4 2 31 DEDF_TXINFO_FERR TXINFO on First System Bus DED Bus CBN Device Number 04h Address Offset F9 FAh Size 16 bits Default Value 00h Attribute Read Only New Value Latched anytime appropriate FERR register bit is set This register records the ITID and failing chunk corresponding to the first DED detected by system bus interface in the SDC Bits Description 15 9 reserved 0 8 6 DC...

Page 42: ... The register is sticky through reset that is the contents of the register remain unchanged during and following the assertion of X 0 1 RST This allows system recovery software invoked following a forced reset to examine the flags to determine the cause of an error Once set the flags remain set until explicitly cleared by software or a power good reset Bits Description 7 reserved 0 6 PERR observed...

Page 43: ...h Size 8 bits Default Value 00h Attribute Read Write This register provides extended control over the assertion of SERR beyond the basic controls specified in the PCI standard PCICMD register Bits Description 7 reserved 0 6 Assert SERR on Observed Parity Error If set the PXB asserts SERR if PERR is observed asserted and the PXB was not the asserting agent 5 Assert SERR on Received Data with Parity...

Page 44: ...ror detected in GPI Bits Description 7 PCISTS Error Logged This bit is asserted when an error except for a master abort has been logged in the PCI Status register 6 Non Configuration Master Abort This bit is asserted when a master abort occurs on any transaction other than a configuration read or configuration write reported the same as a master abort see PCISTS register 5 Discard Timer Expiration...

Page 45: ...16 requests 0 Illegal AGP Command 2 4 5 4 FERR_GART First Error Status Register for GART Function Number BFN 1 Address Offset 86h Size 8 bits Default Value 00h Attribute Read Write Clear Sticky Yes Locked No These registers record and latch the first error detected in the AGP interface Bits Description 7 4 reserved 0 3 GART Parity Error 2 GART Entry Invalid 1 Illegal Address after GART translation...

Page 46: ...s Locked No These registers record and latch the Address and Command information on the PCI Bus for the first error detected Bits Description 63 46 reserved 0 45 PCI Parity 2nd phase of DAC not defined for non DAC address 44 PCI Parity if DAC this is the parity of the first half of the address 43 40 PCI Command Command of Error 39 0 PCI Address Address Received on Error possible DAC address 2 4 5 ...

Page 47: ...ror Flag This flag is set when the PCI bus reports an error e g data parity error on transactions to from other PCI bus agents This bit remains set until explicitly cleared by software writing a 1 to this bit This bit is only set when the error is reported through the NEPCI Next Error register indicating that the error is not the first error occurrence since the First Error register was last clear...

Page 48: ...parity errors and data parity errors detected in outbound transactions e g Internal Queue Error detected during read by PCI interface Default 0 12 ASAPE Assert SERR on Address Parity Error This bit should always be set to 1 When the WXB detects a PCI Address Parity Error and both SERRE and PERRE are set SERR and SERR_OUT will be signaled Default 0 11 ASDPE Assert SERR on any Data Parity Error If s...

Page 49: ...igured to assert XBINIT or an INTRQ interrupt through the ERRCMD register Default 0 3 PODT PERR Observed on PCI Data Transfer This flag is set if the WXB detects the PERR input asserted and the WXB was not the asserting agent This flag may be configured to assert SERR XBINIT or an INTRQ interrupt through the ERRCMD register Default 0 2 reserved 0 1 PEOD Parity Error on Received PCI Data This flag ...

Page 50: ...e Read Write Clear Sticky These registers record and latch the PCI information sent or received specifically associated with the PCI bus error for the first error detected The recorded data contains the upper or lower AD and C BE and PAR signals Bits Description 39 37 reserved 0 36 PAR 35 32 C BE 31 0 AD 2 5 Performance Monitor Registers 2 5 1 SAC 2 5 1 1 IT_MON_PMD_ 0 to 5 Internal Transaction Pe...

Page 51: ..._MON_PMC_ 0 to 5 Internal Transaction Performance Monitor Config Register Bus CBN Device Number 00h Function 2 Address Offset D0 D7h D8 DFh Size 64 bits each E0 E7h E8 EFh F0 F7h F8 FFh Default Value 0h each Attribute Read Write Sticky No Locked No The IT_MON_PMC_ 0 to 5 Registers specify the configuration of the Internal Transaction Performance Monitors This includes specifying Event Selection Un...

Page 52: ...Reply to Write 1R0 0010b I O Read 1R0 0011b I O Write Deferred Reply 1R1 0011b I O Write Posted 1R0 0101b Purge TC and reserved and Branch Trace Messages 1R1 0101b Outbound Interrupt or Hard Fail Write Completion 1R0 0110b Mem Read 1R1 0111b Memory Write 110 1000b Check Connection 1R0 1010b Cfg Read 1R0 1011b Cfg Write Deferred Reply 1R1 1011b Cfg Write Posted 000 1100b Inbound Interrupt 1R0 1110b...

Page 53: ...isable on falling edge of SAC Event 0 11b Disable on falling edge of SAC Event 1 4 3 Enable Source Selects event that will enable the performance monitor 00b Never Enable 01b Enable Always Disable events overrides this setting and will disable counting 10b Enable on rising edge of SAC Event 0 11b Enable on rising edge of SAC Event 1 2 0 Reload Control Selects event that will control the Reloading ...

Page 54: ...s regardless of issuing agent 14 8 Event Select Selects the event to be monitored 000 0000b Monitoring Disabled 000 0001b System Bus Clocks 000 0010b DBSY Clocks 100 0010b DBSY Events 000 0011b DRDY Clocks 100 0011b DRDY Events 100 0100b DBSY and not DRDY Events 000 0101b TRDY Clocks 100 0101b TRDY Events 000 0110b TRDY asserted when DBUSY asserted clocks 100 0110b TRDY asserted when DBUSY asserte...

Page 55: ...umber 04h Address Offset A0 A7h A8 AFh Size 64 bits each Default Value 0 each Attribute Read Write Two performance monitoring counters with associated event selection and control registers is provided in the SDC component These counters may be configured to track system bus events Event detection may be configured to increment a counter affect performance monitoring pins and issue an interrupt req...

Page 56: ... each Attribute Read Write There are two PMR registers for each PCI bus one for each PMD counter Each PMR register specifies how the event selected by the corresponding PME register affects the associated PMD register P A B MON pins and the INT A B RQ pins Bits Description 7 6 Interrupt Assertion Defines how selected event affects INTRQ assertion Whenever INTRQ is asserted a flag for this counter ...

Page 57: ...the tracking of bus transactions by limiting event detection to those transactions issued by specific agents That is unless otherwise noted for the specific event selected below the agent initiating the bus transaction must match the selection specified here for the transaction to be tracked Note This field is applicable only if the PCI bus is operated in internal arbiter mode If the bus is operat...

Page 58: ...it is used as a overflow detection bit The 39 bit count value allows up to 70 minutes of event collection at 133 MHz Event selection is controlled by the PMC registers Each counter may be stopped started independently using the controls available in the associated PMD register Bits Description 63 40 reserved 0 39 Overflow This bit is asserted when the Event Count bit 38 carries into bit 39 Individ...

Page 59: ... up to 70 minutes of event collection at 133 MHz Event selection is controlled by the PMC registers Each counter may be stopped started independently using the controls available in the associated PMD register Bits Description 63 40 reserved 0 39 Overflow This bit is asserted when the Event Count bit 38 carries into bit 39 38 0 Count Value This register contains the Performance Monitor Data Regist...

Page 60: ...ransfer Cycles 17 16 Pipe or Sideband Request Mask 00b reserved 01b Selects Low Priority 10b Selects High Priority 11b Selects Both 15 14 reserved 0 13 8 Event Select Selects the event to be monitored 00 0000b Monitoring Disabled 00 0001b AGP Read Request Events 00 0010b AGP Write Request Events 00 0011b All AGP Request Events does not include Flush or Fence requests 00 0101b Singe Read that split...

Page 61: ...Reloading of the performance monitor with the value written into the associated PMD register 000b Never Reload 001b Reload when counter overflows 010b Reload when GXB Event 0 Asserted 011b Reload when GXB Event 1 Asserted 100b Reload on GXB Event 0 Asserting edge 101b Reload on GXB Event 1 Asserting edge 2 5 4 5 PCI_PMC PCI Performance Monitor Configuration Register Function Number BFN 1 Address O...

Page 62: ...Y 10 0010b Count PCI clocks data is transferring 7 reserved 0 6 5 Disable Source Selects event that will disable the performance monitor 00b Never Disable 01b Disable when counter overflows 10b Disable on falling edge of GXB Event 0 11b Disable on falling edge of GXB Event 1 4 3 Enable Source Selects event that will enable the performance monitor 00b Never Enable 01b Enable Always with this settin...

Page 63: ...0bAll events 001bRetry for any reason 010bRetry no buffers available inbound read or write transactions only 011bRetry no data available inbound read transactions only 101bLocked 110bDual Address Cycles 20 19 reserved 0 18 17 Issuing Agent Qualifier Monitor only those selected events issued by the following agent 00breserved 01bOutbound Issued by WXB 10bInbound Not issued by WXB 11bAll Issued by a...

Page 64: ...dated by XTPR Update Special Cycle on the system bus The second cycle of the XTPR Update Special Cycle s address determines the value to load into the register Ab 27 24 is the 4 bit XTPR value Ab 23 20 determines which register to update Since the high priority agent reserves the uppermost agent ID bit only Ab 22 20 are used These 3 bits decode to one of the 8 registers Ab 31 is the enable bit for...

Page 65: ...here it can be manipulated by software The selector values for the indirect access registers are listed in Section 2 6 3 Software programs bits 7 through 0 of this register to select the desired internal register The contents of the selected 32 bit register can be manipulated via the I O window register The I O register select register is read write by software and its default is listed in Section...

Page 66: ... issue a single new interrupt message upon receiving an EOI write corresponding to the still asserted interrupt input pin The PID only uses the x APIC EOI register in SAPIC mode Note If multiple redirection entries assign the same vector for more than one interrupt pin each of those pins will be resampled and new interrupt messages issued for those that are still asserted This register must be acc...

Page 67: ...W 00000000_00010000h 22h RTE 9 R W 00000000_00010000h 24h RTE 10 R W 00000000_00010000h 26h RTE 11 R W 00000000_00010000h 28h RTE 12 R W 00000000_00010000h 2Ah RTE 13 R W 00000000_00010000h 2Ch RTE 14 R W 00000000_00010000h 2Eh RTE 15 R W 00000000_00010000h 30h RTE 16 R W 00000000_00010000h 32h RTE 17 R W 00000000_00010000h 34h RTE 18 R W 00000000_00010000h 36h RTE 19 R W 00000000_00010000h 38h RT...

Page 68: ... 40 R W 00000000_00010000h 62h RTE 41 R W 00000000_00010000h 64h RTE 42 R W 00000000_00010000h 66h RTE 43 R W 00000000_00010000h 68h RTE 44 R W 00000000_00010000h 6Ah RTE 45 R W 00000000_00010000h 6Ch RTE 46 R W 00000000_00010000h 6Eh RTE 47 R W 00000000_00010000h 70h RTE 48 R W 00000000_00010000h 72h RTE 49 R W 00000000_00010000h 74h RTE 50 R W 00000000_00010000h 76h RTE 51 R W 00000000_00010000h...

Page 69: ...ID Register Format Register Offset 00h Default Value 00000000h Attribute Read Write Bit s Name Description 31 28 Reserved These four bits are reserved 27 24 ID 3 0 These four bits provide the APIC ID This field is used by the I O APIC unit of the PID In SAPIC or compatibility mode of operation these bits are ignored 23 16 Reserved These 24 bits are reserved 15 DT This bit defines the delivery type...

Page 70: ... offset such as 11h While programming the RTEs it is recommended that the lower half be programmed first followed by the upper half Table 2 9 I O x APIC Arbitration ID Register Format Register Offset 02h Default Value 00000000h Attribute Read Only Bit s Name Description 31 28 Reserved These four bits are reserved 27 24 ARBID APIC Arbitration ID 23 0 Reserved These 24 bits are reserved Table 2 10 I...

Page 71: ...is bit is set when the local x APIC s accepts the level interrupt sent by the PID The RIRR bit is reset when an EOI message is received from the local x APIC 13 POLARITY POLARITY This bit specifies the polarity of each interrupt signal connected to the interrupt pins of the PID A value of 0 means the signal is high active and a value of 1 means the signal is low active In the case of level high ac...

Page 72: ...essor system bus as the destination The way this redirection occurs is independent of platform implementation Otherwise the processor can ignore the least significant bit 000 Fixed APIC Mode This means deliver the signal on the INTR signal of all processor cores listed in the destination field Trigger mode for fixed delivery mode can be edge or level 001 Lowest Priority APIC Mode This means delive...

Page 73: ...y 3 1 1 Processor Coherency Intel processors do not have a specific bit to specify coherency for each transaction Data and code are usually considered fully coherent with respect to other processors and to each other There are exceptions to this such as the WC write combining memory type Data that is marked as WC in the page table will not be coherent between processors The Itanium processor uses ...

Page 74: ...inating from the I O sub system are presented to the system bus for snooping If a processor has the modified dirty data then it provides it on the data bus and the SAC presents this data back to I O If no cache has the data modified then the data is provided by the SDRAMs Writes are presented to the system bus as well This allows a new code or data page to be brought in and the old page to be inva...

Page 75: ...the system perspective There is no ordering relationship between the PCI command streams of an AGP card and its AGP command streams The AGP spec mandates certain ordering rules within each stream that are visible by the graphics card but the order in which the system does the transactions is not specified Therefore the typical producer consumer model can not be guaranteed by doing simple reads and...

Page 76: ... little endian and big endian accesses The chipset does not need to know which mode the processor is in The chipset provides data in the same manner in both cases There is no indication on the system bus which mode the processor is using 3 6 Indivisible Operations 3 6 1 Processor Locks The 460GX chipset supports locks on the system bus done by the processor These locked transactions are either a s...

Page 77: ...d PCI Locks The 460GX chipset does not support inbound locks 3 6 3 Atomic Writes Some system bus operations such as Write 8 bytes Write 16 bytes and Write 32 bytes are indivisible operations on the system bus However since the PCI protocol allows target device to disconnect at any point in a transfer sequence these operations are not indivisible on the PCI bus Furthermore these accesses cannot be ...

Page 78: ...r more processors tie for the lowest value the processor with the lowest processor ID will be selected The 4 XTPR registers in the 460GX chipset are updated when the processor does a special cycle on the bus When the special cycle is decoded the low order 3 bits of the DID are used to determine which register to update Each XTPR register is disabled at reset and requires a special cycle XPTR updat...

Page 79: ... but do not clock the parallel latch 13 Wait 1000 msec for PCI card initialization except in test mode 14 Gain ownership of the PCI bus through arbitration 15 Clock the parallel latch 16 Release ownership of the bus after 480 nsec 3 8 2 Slot Power down and Disable To power down a PCI slot software sets a command bit in a register Then the hot plug logic performs the following steps 1 Set BUSEN ina...

Page 80: ...System Architecture 3 8 Intel 460GX Chipset Software Developer s Manual ...

Page 81: ...mapped by the MAR this means the compatibility PCI bus for the VGA region this means the PCI bus to which VGA is mapped Parallel segment peer to peer accesses are not supported below 1M a PXB will either forward the access to memory or let it be claimed master abort on the PCI bus below it 4 1 1 1 DOS Region The DOS Region is the lowest 640 KB in the address range 0h to 9_FFFFh DOS applications ex...

Page 82: ...atibility bus Figure 4 1 System Memory Address Space 0 A_0000 C_0000 F_0000 Compatibility Area Extended Memory 10_0000 16 MB FEC0_0000 FF00_0000 FE00_0000 Processor 12 MB Chipset 4 MB 1 MB 15 MB 4 GB 16MB 16 TB 4GB System 32 Firmware Processor Chipset Memory Specific System 1_0000_0000 Memory FFF_FFFF_FFFF MB Areas are not drawn to scale Specific Specific FFFF_FFFF PCI Gaps n x 32M Memory Extended...

Page 83: ... each of the major bus interfaces Therefore the SAC does not require a defined response for inbound requests that reach this area the results are unpredictable FEE0_0000 FEEF_FFFF This segment is used to deliver interrupts The chipset claims outbound accesses to this region and will forward reads to PCI 0a to be master aborted and drops the writes Inbound writes to this region are translated to an...

Page 84: ...bound accesses to this region can only occur due to a programming or address parity error Firmware programs both the PXBs and GXBs with the Top of Memory value A programming error that results in a PXB access above the Top of Memory causes the PXB to route the request as if it were to a peer PCI bus Therefore the request goes through the SAC decoder and causes a BINIT A programming error that resu...

Page 85: ... SAC does not post any I O accesses to this range regardless of the state of the I O posting enable bit This is necessary because I O accesses below 100h have historically had ordering side effects e g accesses to the 8259 Interrupt Masks Figure 4 2 Itanium Processor and Chipset specific Memory Space System 16 MB FEC0_0000 FF00_0000 FE00_0000 12 MB Chipset 4 MB Specific FFFF_FFFF Chipset Reserved ...

Page 86: ...it is set I O writes are posted If this bit is not set all I O writes are deferred I O reads are always deferred Note the 460GX chipset does not support ISA expansion aliasing The IFB supports a full I O space decode so the compatibility issue will be drivers that rely on the I O aliasing behavior Historically the 64k I O space actually was 64k 3 bytes For the extra 3 bytes A 16 is asserted The 46...

Page 87: ...cific FFFF_FFFF PCI Gaps n x 32M DOS System C D and E Segments VGA Memory Region FE00_0000 n x 32M High System Firmware PXB GXB allow to interrupt delivery area PXBs may support peer to peer accesses if enabled as memory GAP directed to a logical PCI segment PXB must ignore GXB must BINIT after GART PXB allows only recommended to use to the PXB s own PCI bus must be ignored accesses to other PCI b...

Page 88: ...s LXGB instead of PCIS 7 PCIS 7 FDFF_FFFFh PCIx PCIx PCIS register determines target PCI bus On PCI if MMBASE address MMT then not claimed GXB unclaimed FE00_0000h FE1F_FFFFh undefined undefined This region is reserved FE20_0000h FE3F_FFFFh Expander port 2 or PCI0A Expander port 2 or PCI0A If DEVNPRES 14 0 send to Expander port 2 else send to PCI 0a FE40_0000h FE5F_FFFFh undefined undefined This r...

Page 89: ...ven if that access hits a range to which the PXB would normally respond with DEVSEL Note The only ranges the PXB doesn t claim are MMBASE to MMT FEF0_0000h to FEFF_FFFFh and 4G 16M to 4G If the PCI card initiates a request to any other address it will be sent up as TPA or memory FEF0_0000h to FEFF_FFFFh PCI0a unclaimed Reads are sent to PCI 0a for master abort Writes get No Data response and are d...

Page 90: ...System Address Map 4 10 Intel 460GX Chipset Software Developer s Manual ...

Page 91: ...set supports 1 or 2 memory cards Each card supports up to 8 GB of memory using 128 MB DIMM s 32 GB with 1 GB DIMM s 2 cards provide up to 16 GB of memory 64 GB with 1 GB DIMM s There are 2 independent interfaces to the SAC SDC from the memory subsystem running simultaneously Each memory interface supports 1 card and has a 72 bit datapath and a separate control path Running at 266 MHz each interfac...

Page 92: ...data per transfer with the SDCs at the rate of one cache line every 30ns 2 13 GB s per interface There is a separate address and control bus for each memory port with 1 card on each port These are independent and may be driving addresses at the same time While one bus is driving a read the other could be driving a write from the write queue This allows greater bandwidth and allows writes to be don...

Page 93: ...set configuration registers DIMMs not having SPD will be considered as not present in the system since they are not visible to firmware DIMMs may have a buffer on the DIMM itself The buffer can be used in a registered mode or a pass through mode The 460GX will support both buffered and unbuffered DIMMs It will support the buffered DIMM in the pass through mode not the registered mode Thus the timi...

Page 94: ...and can be transferred in parallel up to the final data transfer on the system bus As 0 and 1 are being transferred 2 and 3 can be started to the left stacks of each card and their data transfer will be done immediately following that of 0 and 1 The SDC buffers the data and sends it to the system bus with no dead cycles SDRAMs have at least two internal banks 64Mb chips will generally have 4 and 2...

Page 95: ... card can be populated in the system 5 2 2 Non uniform Memory Configurations The example in Figure 5 2 has all the memory rows populated and all rows have the same size DIMMs There is no requirement that memory be populated evenly Some stacks may have fewer populated rows than others and the sizes within each stack may differ Performance will be optimal with evenly populated rows Knowing that user...

Page 96: ...ion register with the chipset mapping At the same time Firmware can calculate total system memory 5 5 2 Removing a Bad Row A row of memory may have a chip or DIMM fail If an un correctable error occurs the system will machine check usually resulting in a reset The 460GX will report which row failed During the next re boot or at power on if the memory test fails firmware may map the failing row as ...

Page 97: ...bbing Scrubbing is the operation of walking through all installed DRAM and looking for errors Each line is read and then written back whether there is an error or not Within the SAC there is an engine to generate addresses to be placed in the memory queue These addresses are placed directly into the SAC memory queue and are not snooped on the system bus nor are they checked for address conflicts s...

Page 98: ...Memory Subsystem 5 8 Intel 460GX Chipset Software Developer s Manual ...

Page 99: ...d to a BINIT In the non aggressive mode many errors will be reported as interrupts and not cause BINIT Even in non aggressive mode when the chipset has certain errors and doesn t know what to do with a transaction or seems out of sync across the chips it will BINIT The chipset will report errors at their use instead of their generation Both the processor and the chipset may poison data If the proc...

Page 100: ...ther single or double bit failures to be generated in memory When the data is read the system should correct the data and report the error for single bit errors or report the error for double bit errors while passing bad ECC to the processor 6 1 3 Expander Buses Parity bits are generated and checked independently for each Expander bus For error behavior see Table 6 1 Hard Fail responses are suppor...

Page 101: ...bits of ECC corrupted for each failed chunk of data These are bits 0 and 1 of the ECC bits or bits 63 and 71 if looking at the entire 72 bits of data ECC Data passed to the private data bus will invert all the calculated parity bits associated with the failing chunk thus passing bad parity to the private data bus 6 4 Usage of First error and Next error The first instance of an error is latched in ...

Page 102: ...orce all other errors to appear in NERR thus losing logging information regarding later errors 6 4 2 BERR BINIT Generation When an error occurs that forces BINIT then an enable bit in CONFIG2 is cleared as BINIT is driven to the bus The enable bit is automatically cleared in order to mask further BINIT assertions Software may also explicitly clear the enable bit to prevent BINIT from occurring Whe...

Page 103: ...private bus for data d parity error on the private bus for byte enables e an internal SDC ram parity error f a single bit correctable error on the system bus or g the 2nd or subsequent single bit memory ECC errors that are not recorded by the SDC as the first 1x error On this error software must read the SDC to determine the type of error that was found If the SDC reports only single bit errors th...

Page 104: ...t then BERR is ignored as an input BERR is driven active on the bus for 3 clocks Each time a new BERR assertion is sampled BINIT will be driven unless the error is masked off LOCK Transaction with No Resources Available Set when a LOCK occurs and there are no outbound resources for the transaction Since the lock can t be retried and there is no place to put the transaction it gets dropped and lost...

Page 105: ...a Complete is received for that stack The MAC will detect the following error in its interface with the SAC Memory Card Error This is set on a parity error on the command sent from the SAC The command bus is a 23 bit bus 22 address bits and one parity bit This error is flagged in the MAC when there is bad parity on this bus The bus should always be driven with good parity Parity checking is done e...

Page 106: ...arity errors from the private bus is placed in the buffer with good parity and has a bit set to indicate that the data is uncorrectable If the data is read out of the buffer and parity is bad then an internal alpha hit or other error occurred Simultaneous write one to clear and hardware set When the SDC_FERR register is set it can only be cleared by writing a one to the set bit If on the cycle tha...

Page 107: ...ystem bus errors are recoverable and therefore the system can clear those errors and continue running To do so software must write a one to the Valid bit of the register This will cause the system to retire the ITID and that transaction is now complete Note that these 3 registers are sticky through reset so that the information is preserved After BINIT or reset but not power on the SECTID DEDTID a...

Page 108: ...ss determined To access the memory s address buffer the procedure is slightly different This buffer is directly readable instead of using the indirect approach used by the BIU To read the MIU address do Read ITID from one of the registers above If the ITID is less than or equal to 31 then do a configuration read from BUS CBN Device 1 Function 2 Address 80h 4 ITID This is MEMTID0 register If the IT...

Page 109: ...e the logging register 6 7 Clearing Errors Firmware or the operating system must clear out all the error registers when returning from a BINIT or a reset Leaving error bits set in the error registers will cause the system to flag that an error from an earlier time is still present Firmware should read each FERR and NERR register and log any bits that are set It should then clear those bits and con...

Page 110: ...get an indication is sent to the SAC as to whether there was an error or not on that transfer If multiple lines have a 2x memory ECC error only the first line that was retrieved by the SDC will have the SAC FERR error set Later 2x memory errors are flagged as generic errors For the SAC_FERR generic errors set the SNE bit Therefore if SAC_NERR has the SNE bit set this simply means that the SDC had ...

Page 111: ...ess won t be translated it is likely to be outside a valid memory range thus an Illegal Address error is likely Since this is one operation both bits 2 and 1 of FERR_GART are set Data in the SDC is handled on an 8 byte basis so that poisoned data causes 8 bytes to have bad parity The expander interface in the SAC handles the data on a 4 byte basis Therefore a single 8B data transfer that is on an ...

Page 112: ... or double bit D fails The SDC will never signal that an error was fatal causing BINIT The processor will handle data that it receives with bad ECC The memory will have bad ECC written to it if incoming data is bad Data to the SAC will be handled by the SAC itself Either the SAC will BINIT on seeing bad data or it will pass it on to the xXB via an Expander port Figure 6 1 SAC Error Flow on Data 2b...

Page 113: ...pts there is a driver enable If the driver is disabled then these signals won t be active even if it says Unconditional in the table Figure 6 2 SDC Error Data Flow Check if bad poison ECC of bad chunk Retire Correct if 1x if 2x write to DB with bad parity flag status Set S S D 1b 8b parity 1b 16b parity Check and flag status regenerate new parity if incoming is bad then generate new parity as bad ...

Page 114: ...E PCMD_FERR RSP Bus Transmission Error SDC Unconditional BINIT SDC_FERR RTE FERR_SAC SFE SDCRSP_FERR ITID Parity Error SDC Unconditional BINIT SDC_FERR IPE FERR_SAC SFE PITID_FERR PDB Receive Length Error SDC Unconditional BINIT SDC_FERR RLE DPBRLE_FERR FERR_SAC SFE Nothing PDB Data Parity Error SDC Failing Chunk of Data will be put in memory with bad ECC poisoned Conditional Interrupt SDC_FERR DP...

Page 115: ...Unconditional BINIT FERR_SAC XBE Nothing External XSERR Active SAC Conditional BERR FERR_SAC XSA Nothing BERR Driver Enable LOCK when no resources are available SAC Unconditional BINIT FERR_SAC LTE Nothing Resource Counter Overflow Underflow SAC Unconditional BINIT FERR_SAC RCE Nothing Memory System Protocol Errors SAC MAC Command Parity Error MAC ERR pin asserted on MAC Unconditional BINIT by SAC...

Page 116: ...NTR FERR_PCI Nothing PERR Observed GXB Unconditional XINTR FERR_PCI possibly PCISTS DPE Nothing PCI Parity Error on Address from Card GXB Let card master abort SERR and XINTR if SERRE set if SERRE not set then neither SERR nor XINTR driven PCISTS PE FERR_PCI possibly PCISTS SSE PAC_ERR SERRE PCI Parity Error on Data from Card GXB Data placed into queue with bad parity Conditional PERR PCISTS PE PC...

Page 117: ...a as good to PCI PCISTS SSE ERRSTS 2 Nothing MODES 3 Expander HF Read Cmplt from SAC PXB PXB Set Status Target abort read to card Received in peer to peer PCISTS STA Nothing Expander Par err on IB Read Data PXB Set Status If outbound error handling is enabled then poison data as passed to PCI else then SERR and pass read data as good to PCI ERRSTS 2 PCISTS SSE Nothing MODES 3 Detected as PCI Maste...

Page 118: ...t ERRCMD 5 may need to be set for sufficient error containment since PERR asserted to the card will not prevent the data which had a parity error from being placed in memory 6 11 2 PXB as Master 6 11 2 1 Master Abort If the PXB initiates a PCI transaction and no target responds the PXB will terminate the transaction with a master abort The PXB will wait five PCI clocks after asserting FRAME for a ...

Page 119: ...will wait at least two PCI clocks before re arbitrating for the PCI bus to retry the transaction If the transaction is a write the PXB will retry the transaction until it succeeds If the transaction is a read the PXB will retry the transaction until it succeeds but may allow writes to pass it Note in all of these cases the retries are not considered errors There is no logging or error reporting of...

Page 120: ...he earlier tables 6 11 3 5 Other Violations The PCI specification identifies numerous cases that are violations of the PCI protocol Other than the cases identified above the PXB makes no attempt to check for such violations Response to such violations is undefined This includes but is not limited to MWI to a misaligned non cache line boundary address MWI to an aligned address but with one or more ...

Page 121: ...red So software must handle all errors and then do an EOI to the interrupt controller 6 11 4 2 GXB Errors The GXB will flag the following errors See Table 6 1 for the behavior of each error 6 11 4 2 1 PCI Interface Errors SERR Observed Set when the GXB sees SERR that was asserted by the graphics card This is not set if the GXB drove SERR PERR Observed Set when the GXB sees PERR that was asserted b...

Page 122: ... a new transaction when there are 16 already outstanding this error is flagged Illegal AGP Command Set whenever the GXB receives an unknown or undefined command from the graphics card 6 11 4 2 4 Data Errors AGP Hi priority Write Que Data Parity Error AGP write data was placed in the que with good parity If this error is set then the write que itself was corrupted The GXB will not report this error...

Page 123: ...ics card The parity on the PCI data will be poisoned out to the card as the data is returned 6 11 4 3 Multiple Errors In the case that 2 or more errors occur at the same cycle multiple bits are set in the FERR register This should be an extremely rare case Software can read the register and check that only one bit is set The data that is captured along with the error is indeterminate Since there a...

Page 124: ... in error it will be passed on to the next interface with bad or poisoned parity Data received over the PCI bus that has bad parity will always be sent on to the chipset core with bad parity Note There is no mode in the WXB to forward good parity if the data was received as bad If the data comes in with bad parity it is always sent out with bad parity Note When addressed to the IHPC outbound write...

Page 125: ...ors are recorded through status bits In most cases these errors can be optionally caused to signal the system that the error has occurred Methods for signaling an error include SERR XBINIT and a P A B INTRQ1 interrupt In the case of data parity errors the minimal response is to record the error and to simply forward the data on across the next interface with bad parity Table 6 2 lists the WXB erro...

Page 126: ...set then unmasked errors will result in SERR being signaled Otherwise even unmasked errors will not cause an SERR Whenever the WXB actually signals an SERR the SSE bit in the PCISTS register will be set If another agent has caused an SERR then the SES bit in the FEPCI or NEPCI register will be set Note When multiple errors which cause an SERR assertion occur within a few cycles of each other there...

Page 127: ...of the error persists All the errors that cause such an event are wired together to drive the internal signal Software is expected to reset the bit causing the interrupt in the First Error or Next Error register where the error is recorded In addition software is expected to then clear the INTRQ Asserted bit in the ERRSTS register When this bit is reset INTRQ will be deasserted unless there is ano...

Page 128: ... any way After a target disconnect the WXB will deassert its request signal and wait at least two PCI clocks before re arbitrating for the PCI bus to complete the transfer 6 12 8 1 3 Received Target Retry A PCI target may issue a retry to indicate that it is currently unable to process the transaction Retry is signaled when the target asserts STOP and DEVSEL and does not assert TRDY Retry is actua...

Page 129: ...e read buffers and These conditions are not treated as an error and will not be logged or reported 6 12 8 2 3 Target Retry The WXB will issue a target retry when A read request is to an address that has already been accepted as a delayed transaction i e the request is already being serviced but data has not arrived A read request to this address has not yet been accepted by the WXB as a delayed tr...

Page 130: ...uired PCI protocol 6 12 8 3 PCI Interface Errors Other PCI interface errors that are handled by the WXB are System Error Signaled Set within the FEPCI register when the WXB sees an SERR asserted by another PCI agent This is not set when the WXB drives SERR Discard Timer Expiration Set when the 215 timer expires The timer starts approximately when the data for a delayed read is requested by the WXB...

Page 131: ...entire texture map for the displayed image Processors have the same view of a flat contiguous memory range in their virtual space where a program may have many megabytes of contiguous address space to use The memory pointed to by those virtual addresses will most likely be discontiguous in main memory The processor through page tables and TLBs remaps the contiguous virtual addresses to the discont...

Page 132: ... 39 11 0 GART Table 36b Main Memory Address 24 Bit GART Entry 12b 24b 18b AGP address 39 12 APBASE 39 12 AGP address If less than APBASE Aperture 16b if256 MB of GART space Offset 39 21 0 GART Table 36b Main Memory Address 14 Bit GART Entry 22b 14b 13b AGP address 39 22 APBASE 39 22 AGP address If less than APBASE Aperture 8b if 1 GB GART 6b if 256 MB GART ...

Page 133: ...ic A fetch from local SRAM should take 30 ns or less instead of the roughly 300 500 ns required to get to DRAM from the GXB Both 1 MB and 4 MB SRAMs will be used To get the 1 MB required 2 of these parts are required For systems that don t require the full 1 GB translation space the SRAM scales with the required space If 256 MB of translated graphics area were sufficient then the system could simp...

Page 134: ... from what was written Parity will be done such that the total number of 1 s including the parity bit total to an even number 7 1 2 Programming GART The addresses to load or read the GART itself lie in the chipset specific area below 4 GB There is a 12 MB area for the chipset to use The GART will exist in this range The GART lies at address range FE20_0000h to FE3F_FFFFh GART entries may be read o...

Page 135: ...Traffic from the graphics card may or may not want to be coherent with the system bus For the discussion here coherency means that addresses will appear on the system bus so that the processors may snoop their caches for that address If the texture map or other image data is marked WC by the processor then that data is not coherent Addresses on the bus which hit in a processor s WC buffer are not ...

Page 136: ...the system must ensure visibility or completion of all operations from that device which were generated before that interrupt For PCI device drivers are required to read a status register on the card that caused the interrupt If the card had done a write before the interrupt then the read completion would force the write to have been seen by the system AGP with its hi priority low priority and PCI...

Page 137: ...ry used for graphics may change during run time One application may need only a few megabytes of AGP space and would only get that many bytes of physical space from the o s It would only program the few entries in the GART that it needed A later application might ask for hundreds of MBs of physical memory and then map more entries in the GART When that application finished it could release the phy...

Page 138: ...e to memory independent of whether the LOCK bit is set on the bus However since legacy code may issue a locked transaction to an AGP device the GXB must ensure there is no deadlock in the presence of a lock targeting AGP see Section 3 6 1 for more information on processor locks The lock flow for a single Read Modify Write to the AGP bus is outlined below 1 An outbound Locked Read request is transf...

Page 139: ...nsmits the completion for the Unlock transaction its pseudo lock is released 7 2 6 Address Alignment and Transfer Sizes The AGP specification allows the graphics card to request reads of size 8 64 bytes in eight byte increments or of size 32 to 256 bytes in 32 byte increments Reads and writes are both aligned on any 8 byte boundary There is no concept of cache line aligned or even page aligned The...

Page 140: ...XB delays all inbound reads A Memory Read targeting memory will fetch 8B unless the transaction begins 4B from the end of a cache line in which case the transaction only fetches 4B A Memory Read Line or Memory Read Multiple will always prefetch up to one cache line of data When the read data is available in the GXB the next matching read attempt from the controller is accepted and the data is stre...

Page 141: ...he AGP write data within the SDC Writes to memory use the linear burst ordering provided on the AGP bus The Write and Write Invalidate commands have small differences as follows Write Accumulates posted data until a a cache line boundary is reached or b the master disconnects before forwarding the request to the SAC The SAC therefore deals with a single packet that represents up to a cache line of...

Page 142: ... optional in the specification and is not required to guarantee forward progress For the GXB outbound reads are done in order If a read is retried then all other reads after it will wait until the first has completed 7 2 7 10 Outbound Writes Write Combining The GXB optimizes outbound write performance by combining writes to sequential locations if enabled into a single write burst on the AGP bus T...

Page 143: ...d writes by the processor to the card This table will change as the implementation is completed and should be viewed as a guideline for the graphics card designer for relative performance trade offs Table 7 3 Burst Write Combining Modes Write Command Used Transfer Mode Data Length Combining Supported Memory Write 1X 4 DW Can not be combined with the next access 4 DW Can combine next access if it i...

Page 144: ...y of a read should be 600 900 ns Defining moderately loaded is the difficult part If the GXB queues are backed up servicing many small AGP requests then the latency may be much higher 7 5 GXB Address Map The System Address Map chapter contains a section describing the what the system address map looks like from the perspective of an expander bridge This section is included to explicitly state whic...

Page 145: ...ware must set these two registers to cover the following ranges In High System firmware fixed range from 4G to 4G 16M In first megabyte of Itanium processor specific fixed range from 4G 16M to 4G 17M In Itanium processor specific below the Interrupt region fixed range from 4G 18M to 4G 20M In chipset specific fixed range from 4G 20M to 4G 32M In any of the nx32M PCI spaces Therefore GAPTOP 4G and ...

Page 146: ...AGP Subsystem 7 16 Intel 460GX Chipset Software Developer s Manual ...

Page 147: ...ace A list of the configuration registers specific to hot plug operation follows The default power up value is included in each register description heading All registers return to their default values upon the assertion of XRST or PCI reset for the particular side in question unless otherwise noted in the description The standard PCI Configuration registers are not described here when implemented...

Page 148: ...h B8h Interrupt Pin Interrupt Line 3Ch BCh Miscellaneous Configuration RW Slot ID 40h C0h Hot Plug Features 44h C4h Arbiter SERR status Power Fault SERR status Switch Change SERR status 48h C8h 4Ch CCh Memory Access Index 50h D0h Memory Mapped Register Access Port 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh NOTE The first 64 bytes are predefined in the P...

Page 149: ...Switch Change SERR Status 8 9 VID Vendor Identification Register 8 3 8 1 2 VID Vendor Identification Register Address Offset 00 01h Size 16 bits Default Value 8086h Attributes Read Only The VID Register contains the vendor identification number identifying the manufacturer of the device This 16 bit register combined with the Device Identification Register uniquely identifies any PCI device Writes ...

Page 150: ...onse to IHPC configuration and memory write parity errors When the bit is 1 the IHPC will assert both the Detected Parity Error status bit and the PERR output upon detection of an error When the bit is 0 the IHPC will assert the Detected Parity Error status on an error but will not assert PERR This bit must be set to zero 0 after RST This bit is configurable in the IHPC with the default value zero...

Page 151: ...f parity error handling is disabled as controlled by bit 6 in the command register The default value of this bit in the IHPC is zero 0 14 Signaled System Error This bit is set whenever the IHPC asserts SERR The default value of this bit in the IHPC is zero 0 13 Received Master Abort Not supported Hardwired Value 0 12 Received Target Abort Not supported Hardwired Value 0 11 Signaled Target Abort No...

Page 152: ...ng a more detailed specification of the device function For the IHPC this field indicates a Generic PCI Hot Plug Controller Hardwired Value 04h 7 0 Register level Programming Interface This field identifies a specific programming interface if any that device independent software can use to interact with the device The Interface is not defined Hardwired Value 00h 8 1 8 CLS Cache Line Size Address O...

Page 153: ...des power up software with the ability to build a consistent address map before booting the machine Bits Description 31 8 Base Address Read Write 7 4 Indicate 256 byte Address Space Requested Hardwired Value 0h 3 Not Prefetchable Hardwired Value 0 2 1 Type Located anywhere in 32 bit address space Hardwired Value 00 0 Memory Space Indicator Hardwired Value 0 8 1 12 SVID Subsystem Vendor Identificat...

Page 154: ...ce number in this register Bits Description 15 8 reserved 0 7 4 The PCI device number for the first slot that supports hot plug 3 0 Number of hot plug slots controlled 8 1 17 Miscellaneous Hot Plug Configuration Address Offset 42h 43h Size 16 bits Default Value 0002h 1 Attribute Read Write Write Once Read Only This is a hot plug specific register used to configure many features of the IHPC Bits De...

Page 155: ...ttribute Partial Read Write Bits Description 7 6 reserved 0 5 0 Switch Change SERR Status Slot F is MSB Slot A is LSB Similar to the Power Fault SERR status register but applicable to switch changes when the switch interrupt redirect bit for a slot is set and the associated interrupt mask bit is logic 0 Unlike the Power Fault SERR status register clearing this bit will also clear the associated in...

Page 156: ...mory Mapped Register Access Port Address Offset 54h 57h Size 32 bits Default Value 00000000h Attribute Read Write When the Enable PCI Config Space Access to Hot Plug Registers bit in the Miscellaneous Hot Plug Configuration Register is set this register becomes mapped into the IHPC memory mapped register space at the location pointed to by the Memory Index Register Bits Description 31 0 Memory Map...

Page 157: ... Outputs RW Reserved SerialInput Byte Pointer RW SerialInput Data RO 10h 90h Hot Plug Non Interrupt Inputs RW 14h 94h Reserved Reserved Reserved M66EN 18h 98h 1Ch 9Ch 20h A0h Reserved 24h A4h Slot ID RW 28h A8h Slot Power RW Switch Int Redirect Enable RW 2Ch ACh ExtendedHot Plug Misc RW 30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h ...

Page 158: ... power on a slot and connect it to the bus or disconnect and power down The SOGO bit must be set to start the output sequence The set of usable Enable Slot bits is determined by the strapping values on the P A B HSIL P A B HSOL and P A B HSOC inputs Unsupported slots in a system do not have writeable Enable Slot bits Writing a zero to a Enable Slot bit will clear the associated Slot Power register...

Page 159: ...eral interrupt input Interrupt Pending Set to a logic 1 when an interrupt is generated Cleared when the interrupt is cleared 2 Shift Output Interrupt Pending Clear When read as logic 1 a hot plug interrupt was generated by SOBS changing from 1 to 0 while the Serial Output Interrupt Enable bit was set Writing a logic 1 clears this bit and its interrupt 1 Shift Output Interrupt Enable When set to a ...

Page 160: ...r LED lsb 19 Slot D Amber LED lsb 18 Slot C Amber LED lsb 17 Slot B Amber LED lsb 16 Slot A Amber LED lsb 15 14 reserved 0 13 Slot F Green LED msb 12 Slot E Green LED msb 11 Slot D Green LED msb 10 Slot C Green LED msb 9 Slot B Green LED msb 8 Slot A Green LED msb 7 6 reserved 0 5 Slot F Green LED lsb 4 Slot E Green LED lsb 3 Slot D Green LED lsb 2 Slot C Green LED lsb 1 Slot B Green LED lsb 0 Slo...

Page 161: ...gnal 12 Slot E FAULT PCI Power Fault Signal 11 Slot D FAULT PCI Power Fault Signal 10 Slot C FAULT PCI Power Fault Signal 9 Slot B FAULT PCI Power Fault Signal 8 Slot A FAULT PCI Power Fault Signal 7 6 reserved 0 5 Slot F Hot Plug Switch 0 lever closed board installed 4 Slot E Hot Plug Switch 0 lever closed board installed 3 Slot D Hot Plug Switch 0 lever closed board installed 2 Slot C Hot Plug S...

Page 162: ...0 Slot C FAULT PCI Power Fault Signal 9 Slot B FAULT PCI Power Fault Signal 8 Slot A FAULT PCI Power Fault Signal 7 6 reserved 0 5 Slot F Hot Plug Switch 0 lever closed board installed 4 Slot E Hot Plug Switch 0 lever closed board installed 3 Slot D Hot Plug Switch 0 lever closed board installed 2 Slot C Hot Plug Switch 0 lever closed board installed 1 Slot B Hot Plug Switch 0 lever closed board i...

Page 163: ...yte Pointer RW 8 2 9 General Purpose Output Address Offset 13h Size 8 bits Default Value 00h Attribute Read Write Pwr Good Rst Only These bits are only driven out following SOGO LED cycles Bits Description 7 6 reserved 0 5 0 General Purpose Output bits one bit per supported slot Slot F is MSB Slot A is LSB 8 2 10 Hot Plug Non interrupt Inputs Address Offset 14h Size 32 bits Default Value Attribute...

Page 164: ...bus cannot be powered down through this register the Slot Enable register is used instead The set of usable Slot Power Control bits is determined by the strapping values on the P A B HSIL P A B HSOL and P A B HSOC inputs Unsupported slots in a system do not have writeable Slot Power Control bits Bits Description 7 6 reserved 0 5 Enable Power to Slot F When 1 slot F is powered up When 0 slot F is p...

Page 165: ...he Host cycle Software should not write to reserved IFB configuration locations in the device specific region above address offset 3Fh During a hard reset the IFB sets its internal registers to predetermined default states The default values are indicated in the individual register descriptions The following notation is used to describe register access attributes RO Read Only If a register is read...

Page 166: ...Reserved 80h APIC Base Address Relocation R W 81h Reserved 82h DLC Deterministic Latency Control R W 83h Reserved 84 85h MGPIOC Muxed GPIO Control R W 86 8Fh Reserved 90 91h PDMACFG PCI DMA Configuration R W 92 95h DDMABASE Distributed DMA Slave Base Pointer R W 96 C7h Reserved C8h RTCCFG Real Time Clock Configuration R W C9 CFh Reserved D0 D3h GPIOBA GPIO Base Address Register R W D4h GPIOE GPIO ...

Page 167: ...ion Offset Mnemonic Register Register Access 00 01h VID Vendor Identification RO 02 03h DID Device Identification RO 04 05h PCICMD PCI Command R W 06 07h PCISTS PCI Device Status R W 08h RID Revision Identification RO 09 0Bh CLASSC Class Code RO 0Ch Reserved 0Dh MLT Master Latency Timer R W 0Eh HEDT Header Type RO 0F 1Fh Reserved 20 23h BMIBA Bus Master Interface Base Address R W 24 3Fh Reserved 4...

Page 168: ...r Access 00 01h VID Vendor Identification RO 02 03h DID Device Identification RO 04 05h PCICMD PCI Command R W 06 07h PCISTS PCI Device Status R W 08h RID Revision Identification RO 09 0Bh CLASSC Class Code RO 0Ch Reserved 0Dh MLT Latency Timer R W 0Eh HEDT Header Type RO 0F 1Fh Reserved 20 23h USBBA USB I O Space Base Address R W 24 3Bh Reserved 3Ch INTLN Interrupt Line R W 3Dh INTPN Interrupt Pi...

Page 169: ... Access 00 01h VID Vendor Identification RO 02 03h DID Device Identification RO 04 05h PCICMD PCI Command R W 06 07h PCISTS PCI Device Status R WC 08h RID Revision Identification RO 09 0Bh CLASSC Class Code RO 0C 1Fh Reserved 20 23h BAR Base Address Register R W 24 3Bh Reserved 3Ch IL Interrupt Line RW 3Dh IP Interrupt Pin RO 3E 3Fh Reserved 40h HC Host Configuration RW 41h SCOM Slave Command Port...

Page 170: ...IFB Register Mapping 9 6 Intel 460GX Chipset Software Developer s Manual ...

Page 171: ... SMM code has the option to restart the timer if needed If the SMM handler desires it can halt the timer by setting its enable bit to 0 This will prevent the SMI generation at the next time out 10 3 CD ROM AUTO RUN Feature of the OS Whenever a CD ROM controller is detected in a system the OS may use the auto run feature if enabled to indicate to the user whether a CD ROM has been plugged in into t...

Page 172: ... 5 2 UDMATIM Ultra DMA Timing Register IFB Function 1 PCI Configuration Offsets 4A 4Bh 7 6 5 4 3 2 1 0 Reserved Secondary Drive 1 Ultra DMA Mode Enable SSDE1 Secondary Drive 0 Ultra DMA Mode Enable SSDE0 Primary Drive 1 Ultra DMA Mode Enable PSDE1 Primary Drive 0 Ultra DMA Mode Enable PSDE0 0 Disabled 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 Enabled 15 14 13 12 11 10 9 8 Re...

Page 173: ...ification for more information regarding the IDENTIFY_DEVICE command Table 10 1 Identify Device Information Used for Determining Drive Capabilities Capability Word Offset Bits Field Device Type Fields that Indicate Device Type Device Type 0 15 General Configuration 0 ATA Device 1 ATAPI Device Ultra DMA Fields that Indicate Ultra DMA Drive Capabilities Ultra DMA 53 2 Field Validity 0 the fields rep...

Page 174: ...is not supported DMA 63 10 8 Multi Word DMA Modes Active bit 10 1 Multi Word DMA Mode 2 is active 0 Multi Word DMA Mode 2 is not active bit 9 1 Multi Word DMA Mode 1 is active 0 Multi Word DMA Mode 1 is not active bit 8 1 Multi Word DMA Mode 0 is active 0 Multi Word DMA Mode 0 is not active DMA 63 2 0 Multi Word DMA Modes Supported bit 2 1 Multi Word DMA Mode 2 is supported 0 Multi Word DMA Mode 2...

Page 175: ... does not support any of the above Multi Single DMA Modes Software at this stage needs to determine if at least one of the above modes is supported by the drive Software should initially determine a drive s best Mult Word DMA capability initially If a drive doesn t support multi word DMA Modes 0 or 1 then software should check if single word DMA Mode 2 is supported Table 10 2 Identify Device Infor...

Page 176: ...e 2 is active 0 Single Word DMA Mode 2 is not active bit 9 1 Single Word DMA Mode 1 is active 0 Single Word DMA Mode 1 is not active bit 8 1 Single Word DMA Mode 0 is active 0 Single Word DMA Mode 0 is not active DMA 62 2 0 Single Word DMA Modes Supported bit 2 1 Single Word DMA Mode 2 is supported 0 Single Word DMA Mode 2 is not supported bit 1 1 Single Word DMA Mode 1 is supported 0 Single Word ...

Page 177: ...mum cycle time for that mode 10 5 5 1 Determining a Drive s Best PIO Capability This section describes how to determine a drive s PIO Capabilities The following PIO drive capabilities are supported by the IFB from fastest to slowest PIO4 w IORDY PIO3 w IORDY PIO2 w IORDY PIO2 without IORDY Compatible Drive does not support any of the above PIO Modes Table 10 4 Drive Multi Word DMA Single Word DMA ...

Page 178: ...ing modes are defined by the ATA Specification A drive that reports a given PIO capability must be capable of supporting the minimum cycle time for that mode Note If a drive does not report a PIO cycle time that is consistent with the Target PIO Cycle Time a slower speed should be chosen Table 10 5 Identify Device Information Used for Determining PIO Drive Capabilities Capability Word Offset Bits ...

Page 179: ... Enabled N A DMA not supported PIO3 w IORDY Mode 3 Yes No Disabled Enabled if fixed disk Enabled Enabled N A DMA not supported PIO4 w IORDY Mode 4 Yes No Disabled Enabled if fixed disk Enabled Enabled Single Word DMA Mode 2 PIO0 1 Compatible Mode 2 No special config needed Yes Enabled Enabled if fixed disk Dependson Drive Enabled Single Word DMA Mode 2 PIO2 Mode 2 Yes No Disabled Enabled if fixed ...

Page 180: ...ve Enabled if fixed disk Enabled Enabled E3 B xx11xx11 Mode 3 Mode 0 Depends on Drive Enabled if fixed disk Enabled Enabled Disabled Enabled if fixed disk Disabled Disabled A1 0 0x00xx11 Mode 3 Not Present Depends on Drive Enabled if fixed disk Enabled Enabled Disabled Disabled Disabled Disabled A1 0 0000xx11 Mode 3 Mode 2 Depends on Drive Enabled if fixed disk Enabled Enabled Depends on Drive Ena...

Page 181: ...ve bits 3 0 Primary or bits 7 4 Secondary Resultant Cycle Time Total Clocks Base Operating Freq PIO0 Compatible Default Default C0h 80h 0 30 MHz 900ns 33 MHz 900ns PIO2 SW2 4 clocks 4 clocks D0h 90h 4 30 MHz 256ns 33 MHz 240ns PIO3 MW1 3 clocks 3 clocks E1h A1h 9 30 MHz 198ns 33 MHz 180ns PIO4 MW2 3 clocks 1 clock E3h A3h B 30 MHz 132ns 33 MHz 120ns Table 10 10 Ultra DMA Timing Value Based on Driv...

Page 182: ...t 0Ah MUST be set This will allow PCI Bus Master IDE capable device drivers to recognize the fact that this drive has been identified and configured by the firmware for PCI Bus Master IDE operation Table 10 11 Ultra DMA Multi Word DMA Single Word Transfer Mode Values Drive s Selected Ultra DMA Capability Drive s Selected Non ultra DMA Capability Selected Speed ATA SET_FEATURES Command Set Transfer...

Page 183: ...s have been configured for DMA operation 10 5 8 Settings Checklist The following checklists can be used in determining drive modes Refer to the Determining a Drive s Transfer Rate Capabilities and IFB Timing Settings sections for more information 7 6 5 4 3 2 1 0 Reserved Drive 1 DMA Capable DMACAP1 Drive 0 DMA Capable DMACAP0 Reserved IDE Interrupt Status IDEINTS IDE DMA Error Bus Master IDE Activ...

Page 184: ...A Control Register PCI 48h Ultra DMA Timing Register PCI 4A 4Bh Drive Type Position Best Ultra DMA Mode Best DMA Mode Best PIO Mode IFB Ultra DMA Mode IFB Mode Non Ultra DMA Supported Best DMA Mode is SW2 MW1 MW2 Fast PIO Supported Best PIO Mode Best DMA Mode Drive 0 Fixed Disk Primary Single Ultra DMA Mode 2 Multi Word DMA Mode 2 PIO4 Ultra DMA Mode 2 Mode 4 yes yes Drive 2 ATAPI CDROM Secondary ...

Page 185: ...es Register Type Offset Value Comments PCI Command Register PCI 04h 0005h Ensure that bits 0 and 2 are 1 PCI Master Latency Timer PCI 0Dh System dependent PCI Bus Master IDE Base I O Address PCI 20 23h System dependent Ensure that bit 0 of register value is 1 IDE Timing Register 1 PCI 40 41h E377h Mode config for Primary IDE Timing Register 2 PCI 42 43h A103h Mode config for Secondary Secondary ID...

Page 186: ...t controllers 3 Preserve Ultra DMA 33 configuration across reset states restoring Ultra DMA 33 operation described in Item 2 as necessary Ultra DMA 33 Aware Device Drivers shall I Provide support for PCI Bus Master IDE Operation SFF8038i A Identify system configured for PCI Bus Master IDE operation 1 Identify PCI Bus Master IDE and Ultra DMA 33 capable devices and host controllers 2 Utilize PCI Bu...

Page 187: ... signals an interrupt In response to the interrupt software verifies that the bus is idle and then writes the Stop Bus Master Command It then reads the controller status register to determine if the transfer completed successfully For a detailed description of the Bus Master IDE Status Register refer to the last section of this document called Bus Master IDE Command and Status Registers If the IDE...

Page 188: ...0 after the data transfer is completed as indicated by either bit 0 or bit 2 being set in the IDE Channel s Bus Master IDE Status Register Bit Description 7 Reserved This bit is hardwired to 0 6 Drive 1 DMA Capable DMA1CAP R W 1 Drive 1 is capable of DMA transfers This bit is a software controlled status bit that indicates IDE DMA device capability and does not affect hardware operation 5 Drive 0 ...

Page 189: ... The IDE device generated an interrupt The controller has not reached the end of the physical memory regions This is a valid completion case when the size of the physical memory regions is larger than the IDE device transfer size 0 0 Error condition If the IDE DMA Error bit is 1 there is a problem transferring data to from memory Specifics of the error have to be determined using bus specific info...

Page 190: ...IFB Usage Considerations 10 20 Intel 460GX Chipset Software Developer s Manual ...

Page 191: ...t 00 01h Default Value 8086h Attribute Read Only The VID Register contains the vendor identification number This register along with the Device Identification Register uniquely identifies any PCI device Writes to this register have no effect 11 1 2 DID Device Identification Register Function 0 Address Offset 02 03h Default Value 7600h Attribute Read Only The DID Register contains the device identi...

Page 192: ...does not support disabling its Function 0 bus master capability This bit is hardwired to 1 1 Memory Access Not Implemented The IFB does not support disabling Function 0 access to memory This bit is hardwired to 1 0 I O Space Access Enable Not Implemented The IFB does not support disabling its Function 0 response to PCI I O cycles This bit is hardwired to 1 Bit Description 15 Detected Parity Error ...

Page 193: ... HEDT Header Type Register Function 0 Address Offset 0Eh Default Value 80h Attribute Read Only The HEDT Register identifies the IFB as a multi Function device 8 PERR Response Not Implemented Read as 0 7 Fast Back to Back RO This bit indicates to the PCI Master that IFB as a target is capable of accepting fast back to back transactions This bit is hardwired to 1 6 0 Reserved Bit Description Bit Des...

Page 194: ...erved 0 ACPI Enable When this bit is set to 1 decode of the I O range pointed to by the ACPI base register is enabled and the ACPI power management Function is enabled Note that the APM power management ranges B2 B3h are always enabled and are not affected by this bit Bit Description 7 3 Reserved 2 0 SCI IRQ Map Specifies on which pin the SCI will appear on internally If not using the APIC softwar...

Page 195: ...setting BIOS_WEN will not cause SMIs Once set this bit can only be cleared by a PCIRST 14 11 Reserved 10 3 Reserved Software must preserve these register values 2 BIOS_WEN BIOS Write Enable When this bit is set to a 1 writes to firmware BIOS ranges are allowed When this bit is a 0 writes to firmware BIOS ranges are not allowed and write cycles will be master aborted on PCI There is no protection o...

Page 196: ...2 Serial IRQ Frame Size These bits select the frame size used by the Serial IRQ logic The default is 0100b indicating a frame size of 21 17 4 These bits are readable and writeable however the only programmed value supported by the IFB is 0100b All other frame sizes are unsupported 1 0 Start Frame Pulse Width These bits define the Start Frame pulse width generated by the Serial Interrupt control lo...

Page 197: ... data within 1 ms of the cycle s completion the IFB asserts SERR clears the delayed transaction and sets this bit If either bit 3 of 82h or bit 8 of 4h is not set then this bit will not get set and SERR will not be generated The IFB will still discard the delayed transaction cycle The bit can be cleared by writing 1 to it via software 14 1 Reserved 0 ECC SERR Enable When this bit is a 1 it enables...

Page 198: ...fset 92 93h CH0 3 94 95h CH5 7 Default Value 0000h Attribute Read Write Bit Description 16 13 Reserved 12 Reserved Must be set to 1 11 Reserved 10 Reserved Must be set to 1 9 Reserved 8 Reserved Must be set to 1 7 Reserved Must be set to 1 6 Reserved Must be set to 1 5 Reserved Must be set to 1 4 Reserved Must be set to 1 3 0 Reserved Bits Description 15 14 Reserved Must be set to 11 13 12 Reserve...

Page 199: ... extended bank are readable and write able default 1 Upper RAM data bytes 38h 3Fh in the extended bank are neither readable nor write able This is used to lock bytes 38h 3Fh in the upper 128 byte bank of RAM Write cycles will have no effect and read cycles will not return an expected value Warning This is a write once register that can only be reset by a hardware reset No software means is possibl...

Page 200: ...cription 31 16 Reserved 15 6 Base Address Provides the 64 bytes of I O space 5 1 Reserved 0 Resource Indicator Tied to 1 to indicate I O space Bit Description 7 1 Reserved 0 GPIO Enable When this bit is set to 1 decode of the I O range pointed to by the GPIO base register is enabled and the GPIO Function is enabled Bit Description 7 Reserved 6 4 Decode Range The following table describes which ran...

Page 201: ...F COM 1 001 2F8 2FF COM 2 010 220 227 011 228 22F 100 238 23F 101 2E8 2EF COM 4 110 338 33F 111 3E8 3EF COM 3 Bit Description Bit Description 7 5 Reserved 4 Decode Range The following table describes which range to decode for the FDD Port Bits Decode Range 0 3F0 3F5 3F7 Primary 1 370 375 377 Secondary 3 2 Reserved 1 0 Decode Range The following table describes which range to decode for the LPT Por...

Page 202: ...ode Range 00 530 537 01 604 60B 10 E80 E87 11 F40 F47 3 MIDI Decode Range The following table describes which range to decode for the Midi Port Bits Decode Range 0 330 331 1 300 301 2 Reserved 1 0 SB16 Decode Range The following table describes which range to decode for the Sound Blaster 16 Port Bits Decode Range 00 220 233 01 240 253 10 260 273 11 280 293 Bit Description 15 9 Base Address Base Ad...

Page 203: ...h to the LPC Bus 5 MIDI Enable This enables decoding of the MIDI range to the LPC Bus 4 SB16 Enable This enables decoding of the SB16 range to the LPC Bus 3 FDD Enable This enables decoding of the FDD range to the LPC Bus 2 LPT Enable This enables decoding of the LPT range to the LPC Bus 1 COM B Enable This enables decoding of the COMB range to the LPC Bus 0 COM A Enable This enables decoding of t...

Page 204: ...12 KB of the FWH memory range starting at 4 GB 512 KB FFF80000H to the top 4 GB FFFFFFFFH as well as register space starting at 4 GB 4MB 512KB FFB80000h to the top 4 GB 4MB FFBFFFFFh In addition the upper 128 KB of this range is shadowed at the top of 1 MB 000E0000H 000FFFFFH The enable for this range is controlled through bit 7 of the FWH Decode Enable Register at E3H 27 24 FWH_F0_IDSEL This dict...

Page 205: ...FFFFH as well as register space starting at 4 GB 4MB 3 5MB FF880000h to 4 GB 4MB 3MB FF8FFFFFh The enable for this range is controlled through bit 1 of the FWH Decode Enable Register at E3H 3 0 FWH_C0_IDSEL This dictates the IDSEL of 512 KB of the FWH memory range starting at 4 GB 4 MB FFC00000H to 4 GB 3 5 MB FFC7FFFFH as well as register space starting at 4 GB 4MB 4MB FF800000h to 4 GB 4MB 3 5MB...

Page 206: ...n Block Mode The Request Register status for DMA1 and DMA2 is output on bits 7 4 of a Status Register read Bit Description 7 6 DMA Transfer Mode Each DMA channel can be programmed in one of four different modes Bits 7 6 Transfer Mode 00 Demand Mode 01 Single Mode 10 Block Mode 11 I Cascade Mode 5 Address Increment Decrement Select 0 Increment 1 Decrement 4 Auto initialize Enable 1 Enable 0 Disable...

Page 207: ...Value Bit 3 0 1111 Bit 7 4 0000 CPURST or Master Clear Attribute Read Write A channel s mask bit is automatically set to 1 when the Current Byte Word Count Register reaches terminal count unless the channel is programmed for auto initialization Setting bits 3 0 to 1 disables all DMA requests until a clear mask register instruction enables the requests Note that masking DMA channel 4 DMA controller...

Page 208: ...ter is automatically incremented or decrement after each transfer This register is read written in successive 8 bit bytes The programmer must issue the Clear Byte Pointer Flip Flop command to reset the internal byte pointer and correctly align the write prior to programming the Current Address Register Auto initialize takes place only after a TC Bit Description 7 4 Channel Request Status When a va...

Page 209: ...ddress DMA Channel 0 087h DMA Channel 5 08Bh DMA Channel 1 083h DMA Channel 6 089h DMA Channel 2 081h DMA Channel 7 08Ah DMA Channel 3 082h Default Value Undefined CPURST or Master Clear Attribute Read Write This register works in conjunction with the Current Address Register After an auto initialization this register retains the original programmed value Auto initialize takes place after a TC 11 ...

Page 210: ...ttribute Write Only A write to Initialization Command Word 1 starts the interrupt controller initialization sequence Addresses 020h and 0A0h are referred to as the base addresses of CNTRL 1 and CNTRL 2 respectively An I O write to the CNTRL 1 or CNTRL 2 base address with bit 4 equal to 1 is interpreted as ICW1 For IFB based systems three I O writes to base address 1 must follow the ICW1 The first ...

Page 211: ... initialization sequence to ICW1 ICW2 ICW3 and ICW4 the controller base address is used to write to OCW2 and OCW3 Bit 4 is a 0 on writes to these registers A 1 on this bit at any time will force the interrupt controller to interpret the write as an ICW1 The controller will then expect to see ICW2 ICW3 and ICW4 3 Edge Level Bank Select LTIM This bit is disabled Its Function is replaced by the Edge ...

Page 212: ...gher priority input does not affect the interrupt request lines of lower priority Unlike status reads of the ISR and IRR for reading the IMR no OCW3 is needed The output data bus contains the IMR when an I O read is active and the I O address is 021h or 0A1h OCW1 All writes to OCW1 must occur following the ICW1 ICW4 initialization sequence since the same I O ports are used for OCW1 ICW2 ICW3 and I...

Page 213: ...sked When a 0 is written to any bit in this register the corresponding IRQx is unmasked Note that masking IRQ2 on CNTRL 1 also masks the interrupt requests from CNTRL 2 which is physically cascaded to IRQ2 Bit Description 7 5 Rotate and EOI Codes R SL EOI These three bits control the Rotate and End of Interrupt modes and combinations of the two Bits 7 5 Function Bits 7 5 Function 001 Non specific ...

Page 214: ...n Service Register ISR and the Interrupt Request Register IRR When bit 1 0 bit 0 does not affect the register read selection When bit 1 1 bit 0 selects the register status returned following an OCW3 read If bit 0 0 the IRR will be read If bit 0 1 the ISR will be read Following ICW initialization the default OCW3 port address read will be read IRR To retain the current selection read ISR or read IR...

Page 215: ...evel Triggered mode 2 IRQ10 ECL 0 Edge Triggered mode 1 Level Triggered mode 1 IRQ9 ECL 0 Edge Triggered mode 1 Level Triggered mode 0 Reserved Must be 0 Bit Decription 7 6 Counter Select The Read Back Command is selected when bits 7 6 are both 1 Bit 7 6 Function Bit 7 6 Function 00 Counter 0 select 10 Counter 2 select 01 Counter 1 select 11 Read Back Command 5 4 Read Write Select The Counter Latc...

Page 216: ...perations for other counters may be inserted between the reads Note that the Timer Counter Bit Description 7 6 Read Back Command When bits 7 6 11 the Read Back Command is selected during a write to the Timer Control Word Register Following the Read Back Command I O reads from the selected counter s I O addresses produce the current latch status the current latched count or both if bits 4 and 5 are...

Page 217: ...ther an I O read after a counter latch command or after a Read Back Command and reading the status byte following a Read Back Command Bit Description 7 Counter OUT Pin State 1 Pin is 1 0 Pin is 0 6 Count Register Status This bit indicates when the last count written to the Count Register CR has been loaded into the counting element CE 0 Count has been transferred from CR to CE and is available for...

Page 218: ...e any pending NMI sources The CPU s NMI input logic will then register a new NMI 11 2 4 1 Nmisc Nmi Status and Control Register I O I O Address 061h Default Value 00h Attribute Read Write This register reports the status of different system components controls the output of the speaker counter Counter 2 and gates the counter output that drives the SPKR signal Bit Description 7 SERR NMI Source Stat...

Page 219: ...fy the contents of this register without considering the effects on the state of the other bits 11 2 5 2 RTCD Real time Clock Data Register I O I O Address 071h Default Value Undefined Attribute Read Write The data port for accesses to the RTC standard RAM bank Bit Description 7 NMI Enable 1 Disable generation of NMI 0 Enable generation of NMI 6 0 Real Time Clock Address Used by the Real Time Cloc...

Page 220: ...Advanced Power Management Control Port I O I O Address 0B2h Default Value 00h Attribute Read Write This register passes data APM Commands between the OS and the SMI handler In addition writes can generate an SMI The IFB operation is not effected by the data in this register Bit Description 7 Reserved 6 0 Real Time Clock Extended Address Latched by the Real Time Clock to address memory locations wi...

Page 221: ...g a one to this bit position This bit is not affected by a hard reset caused by a CF9 write 14 12 Reserved 11 PWRBTNOR_STS This bit is set any time a Power Button Override Event occurs The override event occurs when the power button is pressed for 4 consecutive seconds The power button override will cause an unconditional transition to the S5 state as well as set the AFTERG3 bit The firmware or SC...

Page 222: ...f this bit must be maintained even through a G3 state The IFB will not resume from RTC after power failure RSMRST low even if this bit is set This bit is automatically cleared by a power button override The IFB can resume from RTC if only PWROK goes low with RSMRST high Upon reset this bit is undefined 9 Reserved 8 PWRBTN_EN This bit is set to 1 to enable the setting of the PWRBTN_STS bit to also ...

Page 223: ...owever the last written value will be readable For example if software writes 111 reserved value IFB will stay in the ON state but the next read to the SLP_TYP field will return 111 not 000 Upon reset this bit is undefined 9 3 Reserved 2 GBL_RLS This bit is used by the ACPI software to generate an SMI to the firmware Firmware has corresponding enable and status bits to control its ability to recei...

Page 224: ... the General Purpose 0 Enable Register then the setting of this bit will generate an SCI This bit is set by hardware and can only be cleared by writing a 1 to this bit position 0 THRM_STS This is the thermal interrupt status bit This bit gets set anytime the THRM signal is driven active as defined by the THRM_POL bit Additionally if the THRM_EN bit is set then the setting of the THRM_STS bit will ...

Page 225: ...bles an SCI to be generated on a NMI event Upon power up this bit is set to 0 0 THRM_EN This is the thermal enable bit When this bit is set an active level assertion of the THRM signal as defined by the THRM_POL bit will set the THRM_STS bit and generate a power management event an SCI or SMI Upon power up this bit is set to 0 Bit Description Bit Description 15 9 Reserved 8 0 GPIO_STS Each bit cor...

Page 226: ...tarted if SWSMI_TMR_EN bit is set to 0 before the timer expires the timer will not expire and the SMI will not be generated The default for this bit is 0 6 1MIN_EN Enables the 1 minute timer 1 17s to count When it reaches its timeout it will generate an SMI 5 Reserved 4 BIOS_EN Enables the generation of SMI when ACPI software writes a 1 to the GBL_RLS bit 3 EOS End of SMI This bit controls the arb...

Page 227: ... on the current state If in the S0 C0 S0 C1 or S0 C2 states An SMI event will be generated If in an S1 state then a Wake event will be generated and SMI will also be generated If in an S3 S5 state a Wake event will be generated but no SMI will be generated This bit is only set by hardware and can only be reset by writing a one 7 SWSMI_TMR_STS This bit will be set to 1 by the hardware when the Soft...

Page 228: ...rammed to be a GPIO 23 20 Reserved 19 16 Mux Output When set to a 0 the muxed GPIO pin is programmed as an input When set to 1 the muxed GPIO pin is programmed as an output In the GPO mode this bit cannot be changed once the GP Lock bit is set The setting of this bit only has effect if the muxed GPIO is programmed to be a GPIO 15 9 Reserved 8 0 Output When set to a 0 the GPIO pin is programmed as ...

Page 229: ...will be tri stated when the pin is to be driven to a 1 and driven when the pin is to be driven to a 0 The setting of this bit has no effect if the pin is programmed as an input This bit cannot be changed once the GP Lock bit is set The value of this bit only has meaning if the muxed GPIO is enabled as a GPIO 23 20 Reserved 19 16 Muxed TTL When set to a 1 and the data bit is programmed as an output...

Page 230: ...a bit cannot be changed Once this bit is set it can only be cleared by a PCIRST Once this bit is set all other register bits at this bit location cannot be changed 23 20 Reserved 19 16 Muxed Lock When set and the pin is programmed as an output the data bit cannot be changed Once this bit is set it can only be cleared by a PCIRST Once this bit is set all other register bits at this bit location can...

Page 231: ... 0 Pulse When set to a 1 and the data bit after the invert bit is programmed as an input a 0 to 1 transition that is longer than 2 RTC clocks will cause the data bit to be set A 1 to 0 transition will not clear the bit Only a write of 1 to the data bit can clear the data bit If the data bit is not set to an output this value of this bit has no effect When cleared edge triggering is not performed T...

Page 232: ...LPC FWH Interface Configuration 11 42 Intel 460GX Chipset Software Developer s Manual ...

Page 233: ...d Ultra DMA 33 synchronous DMA Functionality Table 12 1 PCI Configuration Registers Function 1 IDE Interface Configuration Offset Mnemonic Register Register Access 00 01h VID Vendor Identification RO 02 03h DID Device Identification RO 04 05h PCICMD PCI Command R W 06 07h PCISTS PCI Device Status R W 08h RID Revision Identification RO 09 0Bh CLASSC Class Code RO 0Ch Reserved 0Dh MLT Master Latency...

Page 234: ...sters Bit Description 15 0 Vendor Identification Number This is a 16 bit value assigned to Intel Bit Description 15 0 Device Identification Number This is a 16 bit value assigned to the IFB IDE Controller Function Bit Description 15 10 Reserved 9 Fast Back to Back Enable FBE This bit is hardwired to 0 8 SERR Enable This bit is hardwired to 0 7 Wait Cycle Control This bit is hardwired to 0 6 Parity...

Page 235: ...tware sets MAS to 0 by writing a 1 to this bit 12 Received Target Abort Status RTA R WC When the Bus Master IDE interface Function is a master on the PCI Bus and receives a target abort this bit is set to a 1 Software sets RTA to 0 by writing a 1 to this bit 11 Signaled Target Abort Status STA R WC This bit is set when the IFB IDE interface Function is targeted with a transaction that the IFB term...

Page 236: ...erface Base Address Register Function 1 Address Offset 20 23h Default Value 00000001h Attribute Read Write This register selects the base address of a 16 byte I O space to provide a software interface to the Bus Master Functions Only 12 bytes are actually used 6 bytes for primary and 6 bytes for secondary This register selects the base address of a 16 byte I O space to provide a software interface...

Page 237: ...nguish between the cables and the 0 1 denotations distinguish between master 0 and slave 1 Bit Description 15 0 Subsystem Vendor ID Bit Description 15 0 Subsystem ID Bit Description 15 IDE Decode Enable IDE 1 Enable 0 Disable When enabled I O transactions on PCI targeting the IDE ATA register blocks command block and control block are positively decoded on PCI and driven on the IDE interface When ...

Page 238: ...ive Select 1 TIME1 When cleared accesses to the data port will use compatible timings for this drive When set and bit 14 cleared accesses to the data port will use bits 13 12 for the IORDY sample point and bits 9 8 for the recovery time When set and bit 14 set accesses to the data port will use the IORDY sample point and recover time specified in the slave IDE timing register 3 DMA Timing Enable O...

Page 239: ... channel Bits 5 4 Number of Clocks 00 4 01 3 10 2 11 1 3 2 Primary Drive 1 IORDY Sample Point PISP1 This field selects the number of PCI clocks between PDIOx assertion and the first PIORDY sample point for the slave drive on the primary channel Bits 3 2 Number of Clocks 00 5 01 4 10 3 11 2 1 0 Primary Drive 1 Recovery Time PRTC1 This field selects the minimum number of PCI clocks between the last ...

Page 240: ...PCICLK 10 CT 2 PCICLK RP 4 PCICLK 11 Reserved 11 10 Reserved 9 8 Secondary Drive 0 Cycle Time SCT0 These bit settings determine the minimum data write strobe Cycle Time CT and minimum Ready to Pause time RP 00 CT 4 PCICLK RP 6 PCICLK 01 CT 3 PCICLK RP 5 PCICLK 10 CT 2 PCICLK RP 4 PCICLK 11 Reserved 7 6 Reserved 5 4 Primary Drive 1 Cycle Time PCT1 These bit settings determine the minimum data write...

Page 241: ...ibute Read Write This register enables disables bus master capability for the IDE Function and provides direction control for the IDE DMA transfers This register also provides bits that software uses to indicate DMA capability of the IDE device Table 12 2 Ultra DMA 33 Timing Mode Settings Cycle Time Bit Settings Ultra DMA 33 Timing Modes Mode 0 120 ns Mode 1 90 ns Mode 2 60 ns 00 01 10 Table 12 3 ...

Page 242: ... Status Register Bit Description 7 Reserved This bit is hardwired to 0 6 Drive 1 DMA Capable DMA1CAP R W 1 Drive 1 is capable of DMA transfers This bit is a software controlled status bit that indicates IDE DMA device capability and does not affect hardware operation 5 Drive 0 DMA Capable DMA0CAP R W 1 Drive 0 is capable of DMA transfers This bit is a software controlled status bit that indicates ...

Page 243: ...erated an interrupt and the Physical Region Descriptors exhausted This is normal completion where the size of the physical memory regions is equal to the IDE device transfer size 1 1 The IDE device generated an interrupt The controller has not reached the end of the physical memory regions This is a valid completion case when the size of the physical memory regions is larger than the IDE device tr...

Page 244: ...IDE Configuration 12 12 Intel 460GX Chipset Software Developer s Manual ...

Page 245: ... Configuration Offset Mnemonic Register Register Access 00 01h VID Vendor Identification RO 02 03h DID Device Identification RO 04 05h PCICMD PCI Command R W 06 07h PCISTS PCI Device Status R W 08h RID Revision Identification RO 09 0Bh CLASSC Class Code RO 0Ch Reserved 0Dh MLT Latency Timer R W 0Eh HEDT Header Type RO 0F 1Fh Reserved 20 23h USBBA USB I O Space Base Address R W 24 3Bh Reserved 2C 2...

Page 246: ...r defines the IFB USB Host Controller Writes to this register have no effect 13 2 3 PCICMD PCI Command Register Function 2 Address Offset 04 05h Default Value 00h Attribute Read Write This register controls access to the I O space registers Bit Description 15 0 Vendor Identification Number This is a 16 bit value assigned to Intel Bit Description 15 0 Device Identification Number This is a 16 bit v...

Page 247: ...Detected Parity Not Implemented Read as 0 14 SERR Status Not Implemented Read as 0 13 Master Abort Status MAS R WC When the Serial Bus module receives a master abort from a PCI transaction MAS is set to a 1 Software sets MAS to 0 by writing a 1 to this bit 12 Received Target Abort Status RTA R WC When the Serial Bus module is a master on the PCI Bus and receives a target abort this bit is set to a...

Page 248: ...If the count expires before the transaction completes IFB initiates a transaction termination as soon as the current transaction is completed The number of clocks programmed in the MLT represents the time slice measured in PCI clocks allotted to IFB after which it must surrender the bus as soon as the current transaction is completed 13 2 8 HEDT Header Type Register Function 2 Address Offset 0Eh D...

Page 249: ...TLN Interrupt Line Register Function 2 Address Offset 3Ch Default Value 00h Attribute Read Write Software programs this register with interrupt information concerning the USB Bit Description 31 16 Reserved Hardwired to 0s Must be written as 0S 15 5 Index Register Base Address Bits 15 5 correspond to I O address signals AD 15 5 respectively 4 1 Reserved Read as 0 0 Resource Type Indicator RTE RO Th...

Page 250: ...his register contains the release of the USB Specification with which this USB Host Controller module is compliant 13 2 16 LEGSUP Legacy Support Register Function 2 PCI Address Offset C0 C1h Default 2000h Attribute Read Write Clear This register provides control and status capability for the legacy keyboard and mouse Functions Bit Description 7 3 Reserved 2 0 Serial Bus Module Interrupt Routing Th...

Page 251: ...use of an SMI Software clears this bit by writing a 1 to it 7 SMI At End Of Pass Through Enable SMIEPTE R W 1 Enable the generation of an SMI when the A20GATE pass through sequence has ended 0 default Disable This may be required if an SMI is generated by a USB interrupt in the middle of an A20GATE pass through sequence and needs to be serviced later 6 Pass Through Status PSS RO 1 A20GATE pass thr...

Page 252: ...maximum packet size that can be used for full speed bandwidth reclamation at the end of a frame This value is used by the Host Controller to determine whether it should initiate another transaction based on the time remaining in the SOF counter Use of reclamation packets larger than the programmed size will cause a Babble error if executed during the critical window at frame end The Babble error r...

Page 253: ...his disconnect and disabling of the port causes bit 1 connect status change and bit 3 port enable disable change of the PORTSC to get set The disconnect also causes bit 8 of PORTSC to reset About 64 bit times after HCReset goes to 0 the connect and low speed detect will take place and bits 0 and 8 of the PORTSC will change accordingly 0 Run Stop RS 1 Run 0 Stop When set to a 1 the Host Controller ...

Page 254: ...ng the packet header portion of the TD When this error occurs the Host Controller clears the Run Stop bit in the Command register to prevent further schedule execution A hardware interrupt is generated to the system 3 Host System Error The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module In a PCI system conditions that ...

Page 255: ...of this register are combined with the frame number counter to enable the Host Controller to step through the Frame List in sequence The two least significant bits are always 00 This requires Dword alignment for all list entries This configuration supports 1024 Frame List entries 13 3 6 SOFMOD Start of Frame SOF Modify Register I O I O Address Base 0Ch Default Value 40h Attribute Read Write This 1...

Page 256: ...ll transition to the attached state and system software will process this as with any status change notification It may take up to 64 USB bit times for the port transition to occur If the Host Controller is in global suspend mode then if any of bits 6 3 1 gets set the Host Controller will signal a global resume Refer to Chapter 11 of the USB Specification for details on hub operation Bit Descripti...

Page 257: ...n this bit is 1 a K state is driven on the port as long as this bit remains 1 and the port is still in suspend state Writing a 0 from 1 causes the port to send a low speed EOP This bit will remain a 1 until the EOP has completed 5 4 Line Status RO These bits reflect the D bit 4 and D bit 5 signals lines logical levels These bits are used for fault detect and recovery as well as for USB diagnostics...

Page 258: ...Universal Serial Bus USB Configuration 13 14 Intel 460GX Chipset Software Developer s Manual ...

Page 259: ... Device Identification RO 04 05h PCICMD PCI Command R W 06 07h PCISTS PCI Device Status R WC 08h RID Revision Identification RO 09 0Bh CLASSC Class Code RO 0C 1Fh Reserved 20 23h BAR Base Address Register R W 24 3Bh Reserved 2C 2Dh SVID Subsystem Vendor ID RO 2E 2Fh SID Subsystem ID RO 30 3Fh Reserved 3Ch IL Interrupt Line RW 3Dh IP Interrupt Pin RO 3E 3Fh Reserved 40h HC Host Configuration RW 41h...

Page 260: ... VID Register defines the IFB Power Management Controller Writes to this register have no effect 14 2 3 PCICMD PCI Command Register Function 3 Address Offset 04 05h Default Value 00h Attribute Read Write This register controls access to the I O space registers Bit Description 15 0 Vendor Identification Number This is a 16 bit value assigned to Intel Bit Description 15 0 Device Identification Numbe...

Page 261: ...he power management I O registers is enabled The base register for the I O registers must be programmed before this bit is set Bit Description Bit Description 15 Detected Parity Not Implemented This bit is hardwired to 0 14 SERR Status Not Implemented This bit is hardwired to 0 13 Master Abort Status Not Implemented This bit is hardwired to 0 12 Received Target Abort Status Not Implemented This bi...

Page 262: ...ters 14 2 8 SVID Subsystem Vendor ID Function 3 Address 2C 2Dh Default Value 0000h Attribute Read only Bit Description 23 16 Base Class Code BASEC 0Ch Serial Bus Controller 15 8 Sub Class Code SCC 05h System Management Bus SMBus Controller 7 0 Programming Interface PI 00h No specific register level programming defined Bit Description 31 16 Reserved Hardwired to 0s Must be written as 0s 15 4 Index ...

Page 263: ... Read Write Bit Description 15 0 Subsystem ID Bit Description 7 0 Interrupt Line The value in this register has no affect on IFB hardware operations Bit Description 7 3 Reserved 2 0 Serial Bus Module Interrupt Routing This field is hardwired to 02h to indicate that PCI interrupt pin PIRQB is used Bit Description 7 2 Reserved 1 SMI_EN When this bit is set any source of an SMB interrupt will instead...

Page 264: ...ce for Function 3 Offset 20h 23h Bit Description 7 0 SMBus Host Slave Command SMBCMD R W Specifies the command values to be matched for SMBus master accesses to the SMBus controller host slave interface SMBus port 10h Bit Description 7 0 SHDW1_ADD Slave shadow address 1 When an SMB master generates an access to the port defined by this register and the SHDW1_EN bit is set in I O space then the SHD...

Page 265: ...ot caused by transaction error This bit is only set by hardware and can only be reset by writing a 1 to this bit position Transaction errors are caused by Illegal Command Field Unclaimed Cycle host initiated Host Device Time out 1 SMBus Interrupt INTER R WC 1 Indicates that the source of SMBus interrupt was the completion of the last host command 0 SMBus interrupt not caused by host command comple...

Page 266: ...rammed in the SMB_CMD_PROT field All necessary registers should be setup prior to writing a 1 to this bit position 0 Writing a zero has no effect This bit always reads zero The HOST_BUSY bit can be used to identify when the SMBus host controller has finished executing the command 5 SMB_IDX_CLR Any read to this register clears the slave interface s internal index pointer to the block SRAM array Thi...

Page 267: ...ield of the SMBus protocol Bit Description 7 0 SMBus Host Command HST_CMD R W This field contains the data transmitted in the command field of SMBus host transaction Bit Description 7 1 SMBus Address SMB_ADDRESS R W This field contains the 7 bit address of the targeted slave device 0 SMBus Read or Write SMB_RW R W 1 Execute a READ command 0 Execute a WRITE command Bit Description 7 0 SMBus Data 0 ...

Page 268: ...le SMBus controller slave interface Functions Bit Description 7 0 SMBus Data 1 SMBD1 R W This register should be programmed with the value to be transmitted in the Data1 field of an SMBus host interface transaction Bit Description 7 0 SMBus Block Data BLK_DAT R W This register is used to transfer data into or out of the block data storage array Bit Description 7 SLV_INT_EN When set to a 1 the gene...

Page 269: ...transaction with an address that matches the host controller slave port of 10h a command field which matches the SMBSLVC register and a match of one of the corresponding enabled events in the SMBSLVEVT register 0 Disable Bit Description Bit Description 7 0 Shadow Command SHDW_CMD RO This field contains the command value which was received during an external SMBus master access whose address field ...

Page 270: ...SM Bus Controller Configuration 14 12 Intel 460GX Chipset Software Developer s Manual ...

Page 271: ...he IFB As a Master Response to Target initiated Termination As a master the IFB responds correctly to the target termination Target Abort Retry or Disconnect IFB as a Target Target initiated Termination The IFB supports three forms of Target initiated Termination Disconnect Retry and Target Abort 15 1 2 Parity Support As a master the IFB generates address parity for read write cycles and data pari...

Page 272: ...enerated by the CPU or bus master 15 2 1 1 Initialization Command Words ICWs Before normal operation can begin each Interrupt Controller in the system must be initialized In the 82C59 this is a two to four byte sequence However for the IFB each controller must be initialized with a four byte sequence This four byte sequence is required to configure the interrupt controller correctly for the IFB im...

Page 273: ...nterrupt EOI The In Service IS bit can be set to 0 automatically following the trailing edge of the second INTA pulse when AEOI bit in ICW1 is set to 1 or by a command word that must be issued to the Interrupt Controller before returning from a service routine EOI command An EOI command must be issued twice with this cascaded interrupt controller configuration once for the master and once for the ...

Page 274: ...ecial Fully Nested Mode This mode will be used in the case of a system where cascading is used and the priority has to be conserved within each slave In this case the special fully nested mode will be programmed to the master using ICW4 This mode is similar to the normal nested mode with the following exceptions When an interrupt request from a certain slave is in service this slave is not locked ...

Page 275: ... output is not used and the microprocessor internal Interrupt Enable flip flop is reset disabling its interrupt input Service to devices is achieved by software using a Poll Command The Poll command is issued by setting P 1 in OCW3 The Interrupt Controller treats the next I O read pulse to the Interrupt Controller as an interrupt acknowledge sets the appropriate IS bit if there is a request and re...

Page 276: ...during a normal IRQ7 routine however the ISR will remain set In this case it is necessary to keep track of whether or not the IRQ7 routine was previously entered If another IRQ7 occurs it is a default 15 2 6 Interrupt Masks 15 2 6 1 Masking on an Individual Interrupt Request Basis Each interrupt request input can be masked individually by the Interrupt Mask Register IMR This register is programmed...

Page 277: ...n acknowledged or interrupt request lines that have not been asserted Only the highest priority interrupt service routine executes at any time The lower priority interrupt services are suspended while higher priority interrupts are serviced The ISR is updated when an End of Interrupt Command is issued Interrupt Mask Register IMR 8 bit register indicating which interrupt request lines are masked Th...

Page 278: ...dled via the PCI configuration space No other registers are associated with the scheme 15 3 1 Protocol Serial interrupt information is transferred using three types of frames a Start Frame one or more IRQ Data frames and one Stop frame There are also two modes of operation Quiet Mode and Continuous Mode 15 3 1 1 Quiet Active Mode To indicate an interrupt the peripheral brings the SERIRQ signal low...

Page 279: ...f the data frames a Stop Frame will be done by the IFB The IFB will drive SERIRQ low for 2 3 PCI clocks The number of clocks determines the next mode If SERIRQ is low for 2 clocks then the next mode is the Quite Mode Any device may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame If SERIRQ is low for 3 clocks then the next mode is the Continuous mode Only ...

Page 280: ...ial count value by two each counter period The counter then asserts IRQ0 when the count value reaches 0 reloads the initial count value and repeats the cycle alternately asserting and negating IRQ0 Counter 1 Refresh Request Signal This counter provides the refresh request signal and is typically programmed for Mode 2 operation The counter negates refresh request for one counter period 838 ns durin...

Page 281: ...procedure for the IFB timer is very flexible Only two conventions need to be observed First for each counter the control word must be written before the initial count is written Second the initial count must follow the count format specified in the control word least significant byte only most significant byte only or least significant byte and then most significant byte Since the Control Word Reg...

Page 282: ...hes the count at the time the command is received This command is used to ensure that the count read from the counter is accurate particularly when reading a two byte count The count value is then read from each counter s Count Register as was programmed by the Control Register The selected counter s output latch OL latches the count at the time the Counter Latch Command is received This count is ...

Page 283: ...f multiple counter status latch operations are performed without reading the status all but the first are ignored The status returned from the read is the counter status at the time the first status Read Back Command was issued Both count and status of the selected counter s may be latched simultaneously by setting both the COUNT and STATUS bits 5 4 00 This is functionally the same as issuing two ...

Page 284: ... 5 1 RTC Registers and RAM The RTC internal registers and RAM are organized as two banks of 128 bytes each called the standard and extended banks The first 14 bytes of the standard bank contain the RTC time and date information along with four registers A D that are used for configuration of the RTC The extended bank contains a full 128 bytes of battery backed SRAM and will be accessible even when...

Page 285: ...ailable when the UIP bit is 0 6 4 Division Chain Select DVx These three bits control the divider chain for the oscillator DV2 DV1 DV0 Function 0 1 0 Normal Operation 1 1 X Divider Reset 1 0 1 Bypass 15 stages test mode only 1 0 0 Bypass 10 stages test mode only 0 1 1 Bypass 5 stages test mode only 0 1 1 Invalid 0 0 0 Invalid 3 0 Rate Select Bits RSx Selects one of 13 taps of the 15 stage divider c...

Page 286: ...vide compatibility with the Motorola 146818B There is not SQW pin on this device This bit is cleared on active RSMRST 2 Data Mode DM The Data Mode DM bit specifies either binary or BCD data representation A one denotes binary and zero denotes BCD This bit is not affected by RSMRST 1 Hour Format HF This bit indicates the hour byte format If one twenty four hour mode is selected If zero twelve hour ...

Page 287: ...efore one of these conditions should be set when adjusting at least two seconds before one of these conditions to ensure proper operation 15 5 3 RTC Interrupts The real time clock interrupt is internally routed within the IFB both to the I O APIC and the 8259 It is mapped to interrupt vector 8 This interrupt is not shared with any other interrupt IRQ8 from the serial stream is ignored 15 5 4 Locka...

Page 288: ...PCI LPC Bridge Description 15 18 Intel 460GX Chipset Software Developer s Manual ...

Page 289: ...ports two versions of the S1 Sleep state In the first the STPCLK signal is active much like the S0 state In the 2nd both STPCLK and SLP are active This puts the CPU in an even lower power state but it cannot maintain cache coherency Entrance to the S1 state is performed by a write to the SLP_EN bit with the appropriate SLP_TYP field Will return to S0 state based on Wake event S4 Suspend to Disk ST...

Page 290: ...er signals Table 16 2 Causes of SMI SMI Event Comment ACPI SMI bit GBL_RLS ACPI sets bit to cause SMI SMM handler clears the bit ACPI I O offset 04h Bit 2 GPIO Assertion When a GPIO is programmed as an input and is set to a 1 an SMI will be generated The bit is cleared when the SMM handler clears the asserting device Overflow of ACPI Timer Time out every 2 34 seconds If SCI_EN is set the timer ove...

Page 291: ...ne wake event set is not recommended This could lock up the system However the power button will always be a wake event If using the S1 Sleep state with SLP active the PCI masters must be prevented from accessing memory because the CPU cannot maintain cache coherence In either of the IFB S1 Sleep states the PCI clock will still be running so the Serial IRQ stream will still be available DMA USB an...

Page 292: ... SLP_EN bit to 1 2 The power button is pressed for 4 seconds This is known as a power button override event In either case the entry to the Soft Off state is done by asserting the SUSB and SUSC signals This will cause the power to be shut and the PWROK signal is assumed to go low Note also that there is no need to enter the Soft Off state gracefully The STPCLK and SUS_STAT signals don t have to be...

Page 293: ...ill transition based on the following table If USB devices are attached setting the AFTERG3 bit to 1 may not be a good idea since the USB devices will lose their configuration during the power failure and may no longer be able to generate a wake events when the power is restored In this case the system may have to always boot after a power failure except if placed into the S5 state due to Power Bu...

Page 294: ...IFB Power Management 16 6 Intel 460GX Chipset Software Developer s Manual ...

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