DOC E10523 Rev.D
Interactive Circuits And Systems Ltd. 2000
35
5.7.13 CR<13> - Trigger
This bit is the internal trigger signal. The “enable” bit CR<14> must have been previously
set, and CR<0> must be set to internal trigger. This bit is automatically cleared after
acquisition is started.
CR<13>
Trigger
READ/WRITE
0
** Automatically cleared **
1
Begin acquisition
5.7.14 CR<14> - Enable
This bit is used to enable acquisition. If external triggering is selected, the acquisition
begins following the next rising edge of the external trigger input, otherwise it starts with the
first valid data after the trigger bit, CR<13>, has been set.
CR<14>
Enable
READ/WRITE
0
ADC acquisition disabled
1
ADC acquisition enabled
5.8 Channel Count Register
Read/Write
This register determines the number of active channels on the board. Only the samples
coming from the active channels are stored in the swing buffer and moved to the selected
output interface. A value (N-1) written in this register will activate channels 1 to N. N must
be an even number. For FPDP transfer, N must be at least 4. The valid range of numbers
that may be programmed to this register is 1 to 31 (3 to 31 for FPDP output).
