DOC E10523 Rev.D
Interactive Circuits And Systems Ltd. 2000
17
5. PROGRAMMING MODEL
The ICS-130 VMEbus Memory Map is shown in Table 5.1 below. The individual bit fields of
the registers are shown in Fig. 4. All programming and control of the ICS-130 is
accomplished through the VMEbus interface. All control register bits that are not defined
have no effect on the operation of the ICS-130, but will always be read as zero. All other
bits are undefined, and may be read as zero or one.
5.1 General Notes
All transfers to and from the ICS-130 control and status registers should be done using D32
VMEbus cycles. The A24 and A32 VMEbus base address is programmed with jumpers
(wire links) on the board as described in section 4. The ICS-130 responds to both
SUPERVISORY and NON-PRIVILEGED VMEbus cycles. Individual bits in the 32 bit
registers are referred to in braces. e.g. ADCCR<0> corresponds to ADC Control Register
bit 0, and ADCDEC<4:0> corresponds to ADC Decimation Register bits 4 through 0.
TABLE 5.1 - ICS-130 Memory Map
REGISTER
OFFSET
TYPE
ADC DATA/DIAGNOSTIC FIFO
BASE + 0x00000 READ ONLY/WRITE ONLY
SCV64
BASE + 0x40000 READ/WRITE
P2 MODULE
BASE + 0x48000 READ/WRITE
STATUS
BASE + 0x50000 READ ONLY
INTERRUPT MASK
BASE + 0x50004 READ/WRITE
CONTROL REGISTER
BASE + 0x50008 READ/WRITE
CHANNEL COUNT
BASE + 0x5000C READ/WRITE
BUFFER LENGTH
BASE + 0x50010 READ/WRITE
ACQUISITION COUNT
BASE + 0x50014 READ/WRITE
DECIMATION
BASE + 0x50018 READ/WRITE
FRAME COUNT
BASE + 0x5001C READ/WRITE
ADC CLOCK
BASE + 0x50020 WRITE ONLY
FPDP CLOCK
BASE + 0x50024 WRITE ONLY
ARM
BASE + 0x50028 WRITE ONLY
ADC RESET
BASE + 0x50030 WRITE ONLY
BOARD RESET
BASE + 0x50034 WRITE ONLY
MASTER CONTROL
BASE + 0x58000 READ/WRITE
