DOC E10523 Rev.D
Interactive Circuits And Systems Ltd. 2000
32
5.7.6 CR<5> - FPDP Word Width
This bit selects the width of the data word used in FPDP transfers. If the unpacked option is
selected, one 16-bit sample is sent in each cycle of the FPDP Strobe (clock) signal; the
sample is aligned to the most significant 16 bits of the 32-bit FPDP data path width (bits
D<31:16>). The natural channel order is maintained (i.e. Channel 1, Channel 2, Channel 3,
etc.). If the packed option is selected, Data is presented on the FPDP in the same format as
in the internal 32-bit memory, i.e. two samples per FPDP Strobe cycle, with the lower-
numbered channel in the most significant 16 bits of the data path.
CR<5>
FPDP Word Width
READ/WRITE
0
Packed format (two samples per Strobe cycle)
1
Unpacked format (one sample per Strobe cycle)
5.7.7 CR<6> ADC Sampling Master Enable
This bit selects the board as a Sampling Master or Slave, when operating in a multiple
ICS-130 board acquisition cluster. In the cluster, only one board can be set as Master. The
Master board sends to all slaves the ADC_CLK (pin 1 and 2 on the P4 connector) and the
Trigger signal (pin 10 on the P4 connector). The ADC_CLK signal is in PECL format.
Slaves receive the ADC_CLK on the P4 connector pin 1 and 2 and the Trigger signal on
pin 10. The Master must be located at one physical end of the P4 Local Bus cable. When
using a single ICS-130, the board should also be configured as Sampling Master.
CR<6>
Mode
READ/WRITE
0
ICS-130 is Slave.
1
ICS-130 is Master.