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DOC E10523 Rev.D
Interactive Circuits And Systems Ltd. 2000
34
5.7.10 CR<9> - FPDP Termination
This bit enables the resistive termination on the FPDP NRDY* and SUSPEND* signals.
These must be connected when using the FPDP interface, on the Master board only. This
applies to single board and multiple board configurations.
CR<9>
FPDP Termination
READ/WRITE
0
FPDP terminations disconnected
1
FPDP terminations connected
5.7.11 CR<11:10> - ADC Mode
These bits select the operating mode of the Sigma-Delta converters. All converters on the
board are programmed to the same mode.
CR<11:10>
ADC Mode
READ/WRITE
0 0
32x oversampling, Band Pass Filter(FCK_IN/63...FCK_IN/33.4 at -
3dB)
0 1
32x oversampling, Low Pass Filter (0...FCK_IN/67 at -3dB)
1 1
16x oversampling, Low Pass Filter (0...FCK_IN/33.5 at -3dB)
5.7.12 CR<12> - Acquisition Mode
This bit selects between the Continuous and Capture modes of acquisition. The user
should refer to section 3.4 for a detailed description of the operation and capabilities of the
board in these modes.
CR<12>
Acquisition Mode
READ/WRITE
0
Continuous
1
Capture