DOC E10523 Rev.D
Interactive Circuits And Systems Ltd. 2000
i
TABLE OF CONTENTS
1.
INTRODUCTION 1
1.1
References 1
2.
GENERAL DESCRIPTION 2
2.1
Board Specifications 4
3.
DETAILED DESCRIPTION 5
3.1
ADC Section 5
3.2
Input Bandwidth and Sample Rate 6
3.3
Clock/Trigger Options 7
3.4
Data Path Selection 7
3.5
Modes of Operation 7
3.6
VMEbus Interface 8
3.7
Cascading Multiple Boards 9
3.8
FPDP Interface 10
3.9
Light-Emitting Diodes 10
4.
HARDWARE PREPARATION 12
4.1
System Configuration 12
4.2
Jumper and Switch Settings 14
4.2.1
VMEbus Base Address Selection 14
4.2.2
P4 Local Bus Interface 16
5.
PROGRAMMING MODEL 17
5.1
General Notes 17
5.2
SCV64 Registers 19
5.3
Performing Block Transfers 25
5.3.1
VMEbus DMA Master 25
5.3.2
VMEbus DMA Slave 26
5.4
ADC Data 26
5.5
Status Register (SR) 27
5.5.1
SR<0> - VMEbus Master IRQ 27
5.5.2
SR<1> - ADC IRQ 27
5.5.3
SR<2> - P2 IRQ 28
5.5.4
SR<3> - IRQ 28
5.5.5
SR<4> - Diag FIFO empty 28
5.6
Interrupt Mask Register (IMR) 29
5.6.1
IMR<0> - VMEbus IRQ Mask 29
5.6.2
IMR<1> - ADC IRQ Mask 29
5.6.3
IMR<2> - P2 Module IRQ Mask 29
5.7
Control Register (CR) 30
5.7.1
CR<0> - Trigger Select 30
5.7.2
CR<1> - Sampling Clock Select 30