DOC E10523 Rev.D
Interactive Circuits And Systems Ltd. 2000
5
3. DETAILED DESCRIPTION
3.1 ADC Section
The ICS-130 board uses 32 16-bit Sigma-Delta ADCs (Analog Devices's AD7723). The
maximum input clock for the Sigma-Delta ADC is 19.2 MHz. Thus, the maximum output rate
(16x oversampling ratio mode) is 1.2 MSamples/sec. When the internal programmable
frequency clock is used, the minimum sampling rate for the ADCs is 1.0 MHz. However, the
ADC data stream may be decimated by up to 256, making the board's effective minimum
output rate 122 Hz. Decimation is accomplished by storing one out of every N samples
where N is programmable from 1 to 256. The full scale input signal level is 2 Vpp differential
(i.e. 2 Vpp on each wire of the differential pair), with an input impedance of 10k
Ω
to ground
on each input wire. Figure 2 shows the input buffer stage for one channel. Two 44-pin
connectors (marked P6 and P7) are provided on the front panel for applying the differential
analog input signals. The inputs may also be driven using a single-ended signal; in this
case, the full-scale input on the driven wire is 4 Vpp. The unused wire should be connected
to ground. If a long cable is used to drive the input, the best arrangement is to use a
shielded twisted pair to drive each channel input, with the undriven wire grounded at the
transmit end of the cable. This scheme takes advantage of the differential input of the
ICS-130 to remove common-mode noise picked up by the cable.
Figure 2 - ICS-130 Analog Input (One Channel Only Shown)