DOC E10523 Rev.D
Interactive Circuits And Systems Ltd. 2000
33
5.7.8 CR<7> - ADC Clock Termination
This bit connects the resistive termination to the P4 ADC_CLK line. This must be enabled
on the End Slave board only, and only in multiple board configurations.
CR<7>
ADC Clock Termination
READ/WRITE
0
Termination disconnected
1
Termination connected
5.7.9 CR<8> - FPDP Master Enable
This bit selects between FPDP Master and FPDP Slave mode, in a multiple board
acquisition cluster when using FPDP output. In the cluster or part cluster connected on a
single FPDP cable, only one board can be set as FPDP Master. The Master board sends to
all slaves the FPDP_CLK (pin 12 and 13 on the P4 connector) and the Data Valid
(DVALID*) signal (pin 15 on the P4 connector). The FPDP_CLK signal is in PECL format.
Slaves receive the FPDP_CLK on the P4 connector pin 12 and 13 and the Data Valid
signal on pin 15.
CR<8>
FPDP Master Enabled
READ/WRITE
0
ICS-130 is FPDP Slave
1
ICS-130 is FPDP Master