DOC E10523 Rev.D
Interactive Circuits And Systems Ltd. 2000
39
5.17 Board Reset Register
Write only
A write to this register masks all interrupts, resets all control register bits to their power-up
defaults (zero) and resets all on-board memory. SCV64 registers and status are unaffected.
The data written to the register is unimportant.
5.18 Master Control Register (MCR)
Read/Write
This register is used to program the FPDP interface configuration.The term FPDP cluster
refers to all ICS-130 boards connected on the same FPDP cable, which may be one or
more. The End Slave is the final ICS-130 board on the cable, in multiple ICS-130
configurations. A Stand-alone Master is the name given to a single ICS-130 configuration.
5.18.1 MCR<09:00> - Frame Length
This field sets the number of words to be sent in a FPDP frame, which is related to the total
number of active channels across all boards. This is value is given by the following
expression:
W = (C x P / 2) - 1
where C = total number of channels selected on all ICS-130 boards in cluster
P = packing factor selected in CR<5>, either 2 for unpacked or 1 for packed
data
The calculated value must be programmed to all ICS-130 boards in the cluster. Note that, in
an FPDP Cluster, all boards except the End Slave must be programmed for 32 active
channels. An End Slave or Stand-alone Master may have any number of active channels
(multiples of two only, minimum of four). The valid range of values for this field is 0 to 1023.
5.18.2 MCR<14:10> - FPDP board address
These bits program the FPDP address for the current board in an FPDP cluster. The range
is 0 to (N-1), where is N is the number of ICS-130 boards connected on the FPDP and P4
cables. The valid range of values for this field is 0 to 31. The FPDP Master or Stand-alone
Master must always have FPDP board address zero.