DOC E10523 Rev.D
Interactive Circuits And Systems Ltd. 2000
28
5.5.3 SR<2> - P2 IRQ
This bit reflects the status of the ADC control unit. When the Swing Buffer swaps, the ADC
control unit will assert this flag, to indicate that new data is available. If ADC interrupts are
enabled, an interrupt request will occur.
SR<2>
P2 Module Interrupt Request
READ ONLY
0
P2 Module is not asserting IRQ
1
P2 Module is asserting IRQ
5.5.4 SR<3> - IRQ
This bit indicates that the ICS-130 is asserting a VMEbus interrupt from either source (i.e.
Master transfer completion or ADC Swing Buffer swap). It is therefore an OR of the state of
bits 0 and 1 of this register.
SR<3>
VMEbus Interrupt Request
READ ONLY
0
VMEbus interrupt is not asserted
1
VMEbus interrupt is asserted
5.5.5 SR<4> - Diag FIFO empty
This bit indicates that the Diagnostics FIFO is empty and is ready for more data.
SR<4>
Diagnostic FIFO Empty
READ ONLY
0
FIFO is not empty
1
FIFO is empty