DOC E10523 Rev.D
Interactive Circuits And Systems Ltd. 2000
ii
5.7.3
CR<2> - Diagnostic Mode Enable 31
5.7.4
CR<3> - P2 Enable 31
5.7.5
CR<4> - FPDP Enable 31
5.7.6
CR<5> - FPDP Word Width 32
5.7.7
CR<6> ADC Sampling Master Enable 32
5.7.8
CR<7> - ADC Clock Termination 33
5.7.9
CR<8> - FPDP Master Enable 33
5.7.10
CR<9> - FPDP Termination 34
5.7.11
CR<11:10> - ADC Mode 34
5.7.12
CR<12> - Acquisition Mode 34
5.7.13
CR<13> - Trigger 35
5.7.14
CR<14> - Enable 35
5.8
Channel Count Register 35
5.9
Buffer Length Register 36
5.10
Acquisition Count Register 36
5.11
Decimation Count Register 37
5.12
Frame Count Register 37
5.13
ADC Clock Frequency Register 37
5.14
FPDP Clock Frequency Register 38
5.15
Arm Register 38
5.16
ADC Reset Register 38
5.17
Board Reset Register 39
5.18
Master Control Register (MCR) 39
5.18.1
MCR<09:00> - Frame Length 39
5.18.2
MCR<14:10> - FPDP board address 39
5.19
Using Diagnostic Mode 40
6.
APPENDICES 42
6.1
Typical Order of Operations for Simple Acquisition 42
6.2
Programming the Internal Clock Generator and FPDP Clock 43
6.2.1
Introduction 43
6.2.2
Programming Summary 43
6.2.3
Control Register 44
6.2.4
Programming Register 44
6.2.5
VCO Programming Constraints 46
6.2.6
Program Register Example 46
6.2.7
Oscillator Programming Example 47
6.3
Analog 1-16 Connector Details 49
6.4
Analog 17-32 Connector Details 49
6.5
P4 Local Bus Connector Details 51
6.6
P3 FPDP Details 53
6.6.1
FPDP Connector Pin Assigments 53
6.6.2
FPDP Signals 56