3-8
3
Figure 3-2 4863 Status Reporting Structure
the Status Byte Register. Unwanted conditions can be blocked from
generating SRQs by setting their corresponding enabling bit to a '0'. The
enabling bits are set by writing the value equal to the sum of all of the
desired logic 1 bits to the enabling register. The value is normally decimal
but can be expressed in HEX, OCTAL or BINARY by prefixing the number
with a #H, #O or #B.
Standard
Event Status
Register
Queue
Not-Empty
Output Queue
7 6 5 4 3 2 1 0
Logical OR
*ESR?
Standard
Event Status
Enable
Register
*ESE <NRf>
*ESE?
&
&
&
&
&
&
&
&
7 6 5 4 3 2 1 0
Operation
Event
Register
Operation Enable Register
&
&
&
&
&
&
Status B
&
&
Operation
Condition
Register
Not
Used
15:10 9 8 7 6 5 4 3 2 1 0
+
Transistion
Register
WTG
Status A
Questionable
Event
Register
Questionable Enable Register
&
&
&
&
15 14....7 6 5 4 3 2 1 0
&
&
&
&
15 Digital Inputs, CH Numbers
15..8 7 6 5 4 3 2 1
Questionable
Condition
Register
Not used
+
Transistion
Register
&
15 14....7 6 5 4 3 2 1 0
15 14....7 6 5 4 3 2 1 0
15 14....7 6 5 4 3 2 1 0
Read by Serial Poll
RQS
MSS
{
{
Read by *STB?
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Service Request
Enable Register
ESB MAV
Status Byte Register
+
&
&
&
&
&
&
&
Note 1 - Execution Error
includes EDR not set and
missing Listen handshake
e r r o r s .
Service
Request
Generation
Power On
External Data Ready
Command Error
Execution Error - Note 1
Query Error
Operation
Complete
Flash Data Corrupted
LLO State
REM State
15:10 9 8 7 6 5 4 3 2 1 0
not used
15:10 9 8 7 6 5 4 3 2 1 0
15:10 9 8 7 6 5 4 3 2 1 0
&
&
EDR #1
**SRE<>, *SRE?
