Hyundai H-HT5115-N Service Manual Download

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SERVICE

DVD 5.1 HOME THEATRE SYSTEM

SERVICE MANUAL

DA918PA

H-HT5115-N

Summary of Contents for H-HT5115-N

Page 1: ...SERVICE DVD 5 1 HOME THEATRE SYSTEM SERVICE MANUAL DA918PA H HT5115 N ...

Page 2: ... 5 2 1 4 DVD SONY HM 313 PUH 6 45 2 1 1 D VD Processor ChipMTK1389 J 46 78 79 124 2 1 2 FLASH MEMORY CMOS 16M 2M 8 1M 16 BIT 125 126 2 1 3 4 Banks x 1M x 16Bit Synchronous DRAM HY57V641620HG 3 PRODUCT SPECIFICATIONS 4 UPGRADING SYSTEM AND CHANGING THE REGION CODE 5 OPERATING INSTRUCTION MAINTENANCE TROUBLESHOOTING 129 6 PROBLEMS AND SOLUTIONS 7 BLOCK DIAGRAM 8 CIRCUIT DIAGRAMS AND WIRING DIAGRAM 1...

Page 3: ...or a metering system that complies with American National Standards institute ANSI C101 1 Leakage Current for Appliances and underwriters Laboratories UL 1270 40 7 With the instrument s AC switch first in the ON position and then in the OFF position measure from a known earth ground metal water pipe conduit etc to all exposed metal parts of the instrument antennas handle brackets metal cabinets sc...

Page 4: ...Before servicing Instruments covered by this service manual and its supplements read and follow the Safety Precautions section of this manual Note If unforeseen circument create conflict between the following servicing precautions and any of the safety precautions always follow the safety precautions Remember Safety First 1 2 1 General Serving Precautions 1 a Always unplug the instrument s AC powe...

Page 5: ...st 2 after removing an electrical assembly equipped with ESD devices place the assembly on a conductive surface such as aluminum foil to prevent electrostatic charge buildup or exposure of the assembly 3 Use only a grounded tip soldering iron to solder or unsolder ESD device 4 Use only an anti static solder removal devices Some solder removal devices not classified as anti static can generate elec...

Page 6: ...ice MT1389J Desktop DVD Player SOC General Datasheet MEDIATEK CONFIDENTIAL NO DISCLOSURE Revision History Revised date Contents of revision Reason for revision Page Remarks 2009 6 18 1st Release Ver 1 0 M e d i a t e k C o n f i d e n t i a l O n l y F o r S A C ...

Page 7: ...ns 3 2 Type 3 3 Usage 3 4 Structure 3 5 Function 4 6 Pin Assignment 19 7 Absolute Maximum Ratings 20 8 Recommend Operation Conditions 20 9 Electrical Characteristics 21 10 Marking on Devices 31 11 Package Description 31 12 Packing Description 33 13 Solder Reflow Condition 38 14 Manual Solder Condition 39 15 Storage Condition 39 16 Other 39 M e d i a t e k C o n f i d e n t i a l O n l y F o r S A ...

Page 8: ...3 1 Applications This present specifications are applied to IC MT1389J 2 Type MT1389J 3 Usage Single Chip IC for DVD Player 4 Structure 0 13um CMOS process Silicon material Monolithic IC 128pin LQFP 3 3 1 2 Dual operation voltages M e d i a t e k C o n f i d e n t i a l O n l y F o r S A C ...

Page 9: ...ideo playback The 108MHz 12 bit video DAC provides users a whole new viewing experience Built in 6ch audio DACs and 2ch audio ADCs could give the variable function solutions High Performance Memory Storage Device As the core of Portable DVD players need more capability to support current multimedia contents The MT1389J provides the interface for the 3 in 1 card reader which supports Memory Stick S...

Page 10: ...ed 2ch Audio ADC for Karaoke High Performance Audio Processor High Performance Progressive Video Processor Support DivX Ultra High Quality 108MHz 12 bit 4 CH TV Encoder USB 2 0 High Speed 5 3 Applications Standard DVD Players DVD Players Home Theater Application Portable DVD Players TV DVD Combo Systems M e d i a t e k C o n f i d e n t i a l O n l y F o r S A C ...

Page 11: ...rface Supports 5 3 3 Volt FLASH interface Supports power down mode Supports additional serial port DVD ROM CD ROM Decoding Logic High speed ECC logic capable of correcting one error per each P codeword or Q codeword Automatic sector Mode and Form detection Automatic sector Header verification Decoder Error Notification Interrupt that signals various decoder errors Provide error correction accelera...

Page 12: ... off unconnected channels Support Macrovision 7 1 L1 Macrovision 525P and 625P CGMS A WSS Closed Caption Progressive Scan Video Automatic detect film or video source Advanced Motion adaptive de interlace Minimum external memory requirement Serial Flash Interface Supports 4Mb 8Mb 16Mb 32Mb 64Mb SPI interface Serial Flash External Interface USB2 0 High Speed Host Memory Stick Secure Digital Memory C...

Page 13: ...e this Implementation in any finished end user or ready to use final product It is hereby notified that a license for such use is required from Dolby Laboratories 2 Macrovision License This device is protected by U S patent numbers 4 631 603 4 577 216 4 819 098 and other intellectual property rights 3 DTS License 1996 2006 DTS Inc 4 Microsoft License This product included technology owned by Micro...

Page 14: ...AC coupled DVD RF signal input RFIN 2 GPI36 125 RFG OPINP Analog Input Main beam RF AC input path 126 RFH OPINN Analog Input Main beam RF AC input path 127 RFA Analog Input RF main beam input A 128 RFB Analog Input RF main beam input B 1 RFC Analog Input RF main beam input C 2 RFD Analog Input RF main beam input D 3 RFE Analog Input RF sub beam input E 4 RFF Analog Input RF sub beam input E 5 AVDD...

Page 15: ...5 LDO2 Analog Output Laser driver output 16 AVDD33_2 Analog Power Analog 3 3V power 17 DMO Analog Output Disk motor control output PWM output 18 FMO Analog Output Feed motor control PWM output 19 TRAY_OPEN Analog Output Tray PWM output Tray open output 20 TRAY_CLOSE Analog Output Tray PWM output Tray close output 21 TRO Analog Output Tracking servo output PDM output of tracking servo compensator 2...

Page 16: ...C 104 R CR PR Analog Red CR PR CVBS or SY 105 AADVSS Ground Ground pin for 2ch audio ADC circuitry 106 AKIN2 GPIO19 Analog 1 Audio ADC input 2 2 Audio Mute 3 MCDATA 4 SPDIF 5 GPIO19 107 ADVCM GPIO20 Analog 1 2ch audio ADC reference voltageC 2 GPIO20 108 AKIN1 GPIO21 Analog 1 Audio ADC input 1 2 Audio Mute 3 AS_DATA3 4 GPIO21 109 AADVDD Power 3 3V power pin for 2ch audio ADC circuitry 110 ADACVSS2 ...

Page 17: ...alog Power 3 3V power pin for audio DAC circuitry 121 AVDD12_1 Analog Power Analog 1 2V power 122 AGND12 Analog Ground Analog Ground General Power Ground 7 56 87 DVDD12 Power 1 2V power pin for internal digital circuitry 81 DVSS12 Ground 1 2V Ground pin for internal digital circuitry 51 71 84 DVDD33 Power 3 3V power pin for internal digital circuitry 50 DVSS33 Ground 3 3V Ground pin for internal d...

Page 18: ... Internal Pull Up 2 SD_D0 set B D E F 3 SD_D2 set C 4 MS_D0 set B D E 5 MS_D2 set C 6 TXD1 7 ASDATA2 8 GPIO6 38 PRST Input PU SMT Power on reset input active low 39 IR Input SR SMT IR control signal input 40 GPIO3 INT InOut 8mA SR SMT 1 INT_ 2 Microcontroller port 3 1 Internal Pull Up 3 SD_CLK set D F 4 MS_CLK set B D E 5 TXD4 6 GPIO3 41 GPIO4 InOut 4mA PD 1 Microcontroller port 3 4 Internal Pull ...

Page 19: ... DRAM data 7 61 DQM0 InOut 2mA PD Data mask 0 62 RD15 InOut 2mA DRAM data 15 63 RD14 InOut 2mA DRAM data 14 64 RD13 InOut 2mA DRAM data 13 65 RD12 InOut 2mA DRAM data 12 66 RD11 InOut 2mA DRAM data 11 67 RD10 InOut 2mA DRAM data 10 68 RD9 InOut 2mA DRAM data 9 69 RD8 InOut 2mA DRAM data 8 70 DQM1 InOut 2mA PD Data mask 1 72 RCLK InOut 4mA PD Dram clock 73 RA11 InOut 2mA PD DRAM address bit 11 M e ...

Page 20: ...Out 2mA PD DRAM address 4 80 RWE Output 2mA PD DRAM Write enable active low 82 CAS Output 2mA PD DRAM column address strobe active low 83 RAS Output 2mA PD DRAM row address strobe active low 85 BA0 InOut 2mA PD DRAM bank address 0 86 BA1 InOut 2mA PD DRAM bank address 1 88 RA10 InOut 2mA PD DRAM address 10 89 RA0 InOut 2mA PD DRAM address 0 90 RA1 InOut 2mA PD DRAM address 1 91 RA2 InOut 2mA PD DR...

Page 21: ...A 8 Microcontroller port 1 5 Internal Pull Up 9 GPIO8 43 GPIO9 InOut 4mA PD 1 SD_CMD set E 2 SD_D0 set A C 3 MS_D0 set A C 4 Y6 Y1 5 ASDATA1 6 ABCK 7 GPIO9 94 GPIO10 InOut 4mA PD 1 SD_D3 set D 2 MS_D3 set D 3 GPIO10 36 GPIO11 InOut 4mA PU 1 SD_D1 set C 2 SD_CMD set B D F 3 MS_BS set D E 4 ABCK 5 ASDATA0 6 Audio Mute 7 RXD1 RXD4 8 Microcontroller port 3 0 Internal Pull Up 9 GPIO11 93 SPDIF GPIO12 I...

Page 22: ...A PU 1 SD_CMD set G 2 MS_BS set F 3 Y2 Y5 4 AS_DATA3 5 GPIO30 48 GPIO31 InOut 4mA PU 1 SD_CLK set G 2 MS_CLK set F 3 Y1 Y6 4 AS_DATA3 5 GPIO31 49 GPIO32 InOut 4mA PD 1 Y0 Y7 2 GPIO32 95 GPIO33 InOut 4mA PD 1 GPIO33 Note 1 The Main column is the main function Alt means alternative function 2 The multi function GPIO pins are set to green characters M e d i a t e k C o n f i d e n t i a l O n l y F o...

Page 23: ...DAC CVBS Y C Component Video System Parser MPEG 1 2 4 JPEG Video Decoder Audio DSP Audio Ouptut Debug Port SDPIF Audio DAC System CPU IR VFD De interlacer CPPM CPRM DRM 32 bit RISC Motor Drive PCM output Internal 6ch Audio DACs 6ch Audio Analog outputs Audio Mic1 Audio Mic2 Internal Audio ADC USB 2 0 High Speed controller MS SD MMC Card Controller USB 2 0 High Full Speed Device MS SD MMC Flash Car...

Page 24: ... AVDD33_1 6 91 RA2 XTALI 7 90 RA1 XTALO 8 INT RF 89 RA0 AGND33 9 88 RA10 V20 10 87 DVDD12 V14 11 86 BA1 REXT GPO5 12 85 BA0 MDI1 13 84 DVDD33 LDO1 14 83 RAS LDO2 15 82 CAS AVDD33_2 16 81 DVSS12 DMO 17 80 RWE FMO 18 USB 79 RA4 TRAY_OPEN 19 78 RA5 TRAY_CLOSE 20 77 RA6 TRO 21 76 RA7 FOO 22 75 RA8 FG GPIO2 23 74 RA9 USB_DM 24 73 RA11 USB_DP 25 72 RCLK VDD33_USB 26 71 DVDD33 VSS33_USB 27 70 DQM1 PAD_VR...

Page 25: ... TSTG Storage Temperature 45 to 150 o C 8 Recommend Operation Condition Symbol Parameters Min Typ Max Unit TOP Operating Temperature 0 70 o C TJ Junction Operation Temp 0 25 115 o C VDD3 3 3V Supply voltage 3 1 3 3 3 6 V VDD2 1 2V Supply voltage 1 15 1 25 1 35 V VDDA Analog Supply voltage 3 1 3 3 3 6 V VIH 3 3V Input voltage high 3 3V IO 2 0 V VIL 3 3V Input voltage low 3 3V IO 0 8 V IIH High leve...

Page 26: ... programmable according to the different application and environment All setting will be defined according to the F W progress and test result 9 2 Built in Audio DAC Characteristics Note All parameters is measured on MediaTek s DVD player reference DVD board the actual performance depends on different PCB design SYMBOL PARAMETER MIN TYP MAX UNIT Vout Output swing level Digital i p level 0 dBFS ADA...

Page 27: ...easure SPDIF output CIC filter right shift 3 bit Test signal 1K Hz sin wave Vpp V Max Input with output THD N 60 dbfs 2 9 DC bias level 1 3 Test signal 1K Hz sin wave Input Vpp Output THD N dBFs 3V 45 2 828V 65 2 75V 65 6 2 5V 66 2V 66 5 1 5V 66 7 1V 66 6 0 5V 67 8 Test signal 2 828 Vpp Input frequency Amp dBFS 1 KHz 0 544 4KHz 0 574 8khz 0 66 16KHz 0 981 20KHz 1 24 22KHz 2 44 M e d i a t e k C o ...

Page 28: ...1008 1008 1008 SYNC TIP 64 64 64 9 5 Video Output Voltage Level High Low Op Impedance Mode IOUT max 19 4152 RREF RREF 2 2 KOhm VOUT max RLOAD IOUT max 1 3237 V RLOAD 150 Ohm VOUT DIN 4095 VOUT max DIN RLOAD 0 0047412 RREF Impedance Mode IOUT max 19 4152 RREF RREF 560 Ohm VOUT max RLOAD IOUT max 1 3 V RLOAD 37 5 Ohm 75 Ohm 75 Ohm VOUT DIN 4095 VOUT max DIN RLOAD 0 0047412 RREF 9 6 Video DAC DC Elec...

Page 29: ...atio 70 dB Power Supply Supply Voltage 3 0 3 3 3 6 V 9 7 RF specification Item Designator Conditions Min Typ Max Unit 3 3V POWER 3 00 3 30 3 60 Volts Enable power down 10 27 50 mA Power Down Mode Chip Reset 90 151 200 mA Reference Voltage V20 Force current 0A 1 85 1 99 2 15 Volts Reference Voltage V14 Force current 0A 1 25 1 39 1 55 Volts MDI1 0Ah 10 APC1 on MDI1 180mV 166 184 202 mV LDO1 0Ah 00 A...

Page 30: ...5h 7C low gain With 10KHz Sin Input 30 54 dB Central Servo Gain MA CSO 06h F0 low gain With 10KHz Sin Input 12 5 14 1 15 5 dB Central Servo Frequency Response MA CSO 06h FF low gain With 10KHz 300KHz Sin Input R G 10kHz G 300Khz 14 21 4 dB Central Servo Common Mode Gain MA CSO MB CSO 06h F0 low gain With 10KHz Sin Input 30 10 dB Central Servo H L Gain MA CSO Toggle 06h bit5 CSOLG With 10KHz Sin In...

Page 31: ...ith 10KHz 300KHz Sin Input R G 10kHz G 300Khz 14 22 7 dB RFL H L Gain I MA LVL Toggle 09h bit1 LVLATN With 10KHz Sin Input 0 3 0 52 0 7 V V RFL H L Gain II SA LVL Toggle 09h bit2 SBADHG With 10KHz Sin Input 2 5 2 77 3 1 V V RFL offset Adjustment step Input Floating Measure LVL Toggle 50h LVLOS 6 0 65 113 140 mV RFL THD MA LVL 08h 7F low gain With 10KHz Sin Input 30 44 dB 9 8 Micro Controller Inter...

Page 32: ...Tf 20 ns PSEN Low to Address Float T7 0 ns AD R 7 0 Inst A D R 7 0 AD R 15 8 t0 t1 t2 t3 t4 t5 t7 t9 t6 t8 t10 t11 ALE PSEN Port 0 Port 2 Program Memory Read Cycle Timing Diagram 9 9 Digital Video Output Interface Parameter Symbol Min Typ Max Units Oscillator Frequency 1 T1 27 MHz YUV digital output delay T2 15 ns HSYNC Rising delay T3 15 ns VSYNC Rising delay T4 15 ns HSYNC Falling delay T5 20 ns...

Page 33: ...rface Timing Diagram 9 10 SPDIF I O Interface Parameter Symbol Min Typ Max Units BCK negative edge to ASDATA valid T1 1 0 3 0 ns ASDATA LRCK input setup T2 3 0 ns ASDATA LRCK input hold T3 1 2 ns ASDATA LRCK BCK ASDATA LRCK t1 ASDATA LRCK SPLIN_BCK t2 ASDATA LRCK input ASDATA LRCK t3 SPDIF Input Output Timing Diagram M e d i a t e k C o n f i d e n t i a l O n l y F o r S A C ...

Page 34: ...ve Read Write Precharge Row Active 6 7 75 Parameter Symbol Min Max Min Max Min Max Units CLK cycle time CAS latency 3 tCC 7 5 7 5 7 5 ns SDRAM input setup time tSS 1 5 1 75 1 75 ns SDRAM input hold time tSH 1 1 1 ns Active to Precharge command period tRAS 42 100K 49 100K 52 100K ns Precharge to Active command period tRP 18 20 20 ns Active to read write command delay tRCD 18 20 20 ns Write recovery...

Page 35: ...it number of clock tRAS tRP tRCD tWR Frequency CAS Latency 49ns 20ns 20ns 7ns 10ns 133MHz 7 5ns 3 7 3 3 1 125MHz 8ns 3 6 3 3 1 100MHz 10ns 2 5 2 2 1 7 5T Unit number of clock tRAS tRP tRCD tWR Frequency CAS Latency 45ns 20ns 20ns 7 5ns 10ns 133MHz 7 5ns 3 6 3 3 1 125MHz 8ns 3 6 3 3 1 100MHz 10ns 2 5 2 2 1 8T Unit number of clock tRAS tRP tRCD tWR Frequency CAS Latency 48ns 20ns 20ns 8ns 10ns 125MH...

Page 36: ...n Devices 11 Package Description 11 1 Package Outline Dimension The bend lead are controlled under the criteria 0 075mm 2 5mil MT1389 FE YYWW JXXL LLLLL Date Code Year Week Lot No MediaTek Logo MTK Production Code Lead Free Product Product Name M e d i a t e k C o n f i d e n t i a l O n l y F o r S A C ...

Page 37: ...Specifications are subject to change without notice MEDIATEK CONFIDENTIAL NO DISCLOSURE 32 M e d i a t e k C o n f i d e n t i a l O n l y F o r S A C ...

Page 38: ...s of terminal is Sn 98 and Bi 2 and thickness is 300 600u inch similar as SnPb 11 4 Package Material Lead frame Cu Epoxy 1033BF Molding compound G700 12 Packing Description Package Pin Ball count EA Tray Tray Box Full Box Q ty Box Carton Full carton Q ty LQFP 128 90 10 900 6 5400 12 1 Tray Description 40ea Hard Tray 150o C resistance M e d i a t e k C o n f i d e n t i a l O n l y F o r S A C ...

Page 39: ...Specifications are subject to change without notice MEDIATEK CONFIDENTIAL NO DISCLOSURE 34 M e d i a t e k C o n f i d e n t i a l O n l y F o r S A C ...

Page 40: ...r B corrugated paper Strength 1176000 PA Box size 355 L 157 W 90 5 H mm Printing Black words warning index 12 5 Side Plank Material 5 Layer AB corrugated paper Strength 1793400 PA Size 405 L 237 W mm Fixture 3 pieces of EPE recyclable material Thickness 20 mm 12 6 Carton Description Material 5 Layer AB corrugated paper Strength 1793400 PA Carton size 558 L 428 W 264 H mm Printing Black words warni...

Page 41: ...thout notice MEDIATEK CONFIDENTIAL NO DISCLOSURE 36 12 7 Packing Flow 90pcs per tray 10 tray Empty tray Aluminum foil bag Pin No 1 direction Label is on top of the Aluminum foil bag M e d i a t e k C o n f i d e n t i a l O n l y F o r S A C ...

Page 42: ...ce MEDIATEK CONFIDENTIAL NO DISCLOSURE 37 Box with the Aluminum foil bag Air cap 6 box per carton Fill with empty box if the quantity is less than 6 box Side plank Label is on top of the BOX M e d i a t e k C o n f i d e n t i a l O n l y F o r S A C ...

Page 43: ...ing and are not meant to specify board assembly profiles Actual board assembly profiles should be developed based on specific process needs and board designs and should not exceed the parameters in Table 1 For example if Tc is 260 o C and time tp is 30 seconds this means the following for the supplier and user For a supplier The peak temperature must be at least 260 o C The time above 255 o C must...

Page 44: ...Specifications are subject to change without notice MEDIATEK CONFIDENTIAL NO DISCLOSURE 39 M e d i a t e k C o n f i d e n t i a l O n l y F o r S A C ...

Page 45: ...on the back of the board for a duration which does not exceed 5 seconds without applying any mechanical stress on the component body It can also be applied under 350 10 o C at the iron bit within 3 seconds please treat it carefully under such condition The chip can t do DIP soldering 15 Storage Condition 15 1 Storage Duration A Notice the Sealing time B 12 monthly and storage condition 40o C 90 R ...

Page 46: ...n products New Top Marking cFeon Top Marking Example Continuity of Specifications There is no change to this data sheet as a result of offering the device as an Eon product Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary where supported Future routine revisions will occur when appropriate and changes will be noted in a ...

Page 47: ...h WP pin High performance program erase speed Page program time 1 3ms typical Sector erase time 90ms typical Block erase time 400ms typical Chip erase time 7 Seconds typical Lockable 128 byte OTP security sector Minimum 100K endurance cycle Package Options 8 pins SOP 200mil body width 8 contact VDFN 8 pins PDIP All Pb free packages are RoHS compliant Industrial temperature Range GENERAL DESCRIPTIO...

Page 48: ...equent versions 2004 Eon Silicon Solution Inc www eonssi com or modifications due to changes in technical specifications 3 EN25F16 Rev F Issue Date 2009 03 16 Figure 1 CONNECTION DIAGRAMS Figure 2 BLOCK DIAGRAM 8 LEAD SOP DIP 8 CONTACT VDFN ...

Page 49: ...ted the devices power consumption will be at standby levels unless an internal erase program or status register cycle is in progress When CS is brought low the device will be selected power consumption will increase to active levels and instructions can be written to and data read from the device After power up CS must transition from high to low before a new instruction will be accepted Hold HOLD...

Page 50: ... Block Sector Architecture Block Sector Address range 511 1FF000 1FFFFF 31 496 1F0000 1F0FFF 495 1EF000 1EFFFF 30 480 1E0000 1E0FFF 479 1DF000 1DFFFF 29 464 1D0000 1D0FFF 463 1CF000 1CFFFF 28 448 1C0000 1C0FFF 447 1BF000 1BFFFF 27 432 1B0000 1B0FFF 431 1AF000 1AFFFF 26 416 1A0000 1A0FFF 415 19F000 19FFFF 25 400 190000 190FFF 399 18F000 18FFFF 24 384 180000 180FFF 383 17F000 17FFFF 23 368 170000 17...

Page 51: ...h 11 176 0B0000h 0B0FFFh 175 0AF000h 0AFFFFh 10 160 0A0000h 0A0FFFh 159 09F000h 09FFFFh 9 144 090000h 090FFFh 143 08F000h 08FFFFh 8 128 080000h 080FFFh 127 07F000h 07FFFFh 7 112 070000h 070FFFh 111 06F000h 06FFFFh 6 96 060000h 060FFFh 95 05F000h 05FFFFh 5 80 050000h 050FFFh 79 04F000h 04FFFFh 4 64 040000h 040FFFh 63 03F000h 03FFFFh 3 48 030000h 030FFFh 47 02F000h 02FFFFh 2 32 020000h 020FFFh 31 01...

Page 52: ...nstruction allows bits to be reset from 1 to 0 Before this can be applied the bytes of memory need to have been erased to all 1s FFh This can be achieved a sector at a time using the Sector Erase SE instruction a block at a time using the Block Erase BE instruction or throughout the entire memory using the Chip Erase CE instruction This starts an internal Erase cycle of duration tSE tBE or tCE The...

Page 53: ... will ignore any input data and program OTP_LOCK bit to 1 user must clear the protect bits before enter OTP mode and program the OTP code then execute WRSR command to lock the OTP sector before leaving OTP mode Write Protection Applications that use non volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity To ad...

Page 54: ...ng Low as shown in Figure 4 The Hold condition ends on the rising edge of the Hold HOLD signal provided that this coincides with Serial Clock CLK being Low If the falling edge does not coincide with Serial Clock CLK being Low the Hold condition starts after Serial Clock CLK next goes Low Similarly if the rising edge does not coincide with Serial Clock CLK being Low the Hold condition ends after Se...

Page 55: ...lect CS must be driven High exactly at a byte boundary otherwise the instruction is rejected and is not executed That is Chip Select CS must driven High when the number of clock pulses after Chip Select CS being driven Low is an exact multiple of eight For Page Program if at any time the input byte is not a full byte nothing will happen and WEL will not be reset In the case of multi byte commands ...

Page 56: ...Memory Type ID7 ID0 Memory Capacity Table 5 Manufacturer and Device Identification OP Code M7 M0 ID15 ID0 ID7 ID0 ABh 14h 90h 1Ch 14h 9Fh 1Ch 3115h Write Enable WREN 06h The Write Enable WREN instruction Figure 5 sets the Write Enable Latch WEL bit The Write Enable Latch WEL bit must be set prior to every Page Program PP Sector Erase SE Block Erase BE Chip Erase CE and Write Status Register WRSR i...

Page 57: ...new instruction to the device It is also possible to read the Status Register continuously as shown in Figure 7 Figure 7 Read Status Register Instruction Sequence Diagram Table 6 Status Register Bit Locations S7 S6 S5 S4 S3 S2 S1 S0 SRP Status Register Protect OTP_LOCK bit note 1 BP2 Block Protected bits BP1 Block Protected bits BP0 Block Protected bits WEL Write Enable Latch WIP Write In Progress...

Page 58: ...truction is no longer accepted for execution In OTP mode this bit is served as OTP_LOCK bit user can read program erase OTP sector as normal sector while OTP_LOCK value is equal 0 after OTP_LOCK is programmed with 1 by WRSR command the OTP sector is protected from program and erase operation The OTP_LOCK bit can only be programmed once Note In OTP mode the WRSR command will ignore any input data a...

Page 59: ...tents at that address is shifted out on Serial Data Output DO each bit being shifted out at a maximum frequency fR during the falling edge of Serial Clock CLK The instruction sequence is shown in Figure 9 The first byte addressed can be at any location The address is automatically incremented to the next higher address after each byte of data is shifted out The whole memory can therefore be read w...

Page 60: ...dge of Serial Clock CLK The instruction sequence is shown in Figure 10 The first byte addressed can be at any location The address is automatically incremented to the next higher address after each byte of data is shifted out The whole memory can therefore be read with a single Read Data Bytes at Higher Speed FAST_READ instruction When the highest address is reached the address counter rolls over ...

Page 61: ... sequence The instruction sequence is shown in Figure 11 If more than 256 bytes are sent to the device pre viously latched data are discarded and the last 256 data bytes are guaranteed to be programmed cor rectly within the same page If less than 256 Data bytes are sent to device they are correctly pro grammed at the requested addresses without having any effects on the other bytes of the same pag...

Page 62: ...ed the Write Enable Latch WEL bit is reset A Sector Erase SE instruction applied to a sector which is protected by the Block Protect BP2 BP1 BP0 bits see Table 3 is not executed Figure 12 Sector Erase Instruction Sequence Diagram Block Erase BE D8h 52h The Block Erase BE instruction sets to 1 FFh all bits inside the chosen block Before it can be accepted a Write Enable WREN instruction must previo...

Page 63: ...he entire duration of the sequence The instruction sequence is shown in Figure 14 Chip Select CS must be driven High after the eighth bit of the instruction code has been latched in otherwise the Chip Erase instruction is not executed As soon as Chip Select CS is driven High the self timed Chip Erase cycle whose duration is tCE is initiated While the Chip Erase cycle is in progress the Status Regi...

Page 64: ...p Select CS Low followed by the instruction code on Serial Data Input DI Chip Select CS must be driven Low for the entire duration of the sequence The instruction sequence is shown in Figure 15 Chip Select CS must be driven High after the eighth bit of the instruction code has been latched in otherwise the Deep Power down DP instruction is not executed As soon as Chip Select CS is driven High it r...

Page 65: ...device is put in the Stand by Power mode If the device was not previously in the Deep Power down mode the transition to the Stand by Power mode is immediate If the device was previously in the Deep Power down mode though the transition to the Standby Power mode is delayed by tRES2 and Chip Select CS must remain High for at least tRES2 max as specified in Table 11 Once in the Stand by Power mode th...

Page 66: ...evice ID values for the EN25F16 are listed in Table 5 If the 24 bit address is initially set to 000001h the Device ID will be read first Figure 18 Read Manufacturer Device ID Diagram Read Identification RDID 9Fh The Read Identification RDID instruction allows the 8 bit manufacturer identification to be read followed by two bytes of device identification The device identification indicates the memo...

Page 67: ...de 3Ah This Flash has an extra 128 bytes OTP sector user must issue ENTER OTP MODE command to read program or erase OTP sector After entering OTP mode the OTP sector is mapping to sector 511 SRP bit becomes OTP_LOCK bit and can be read with RDSR command Program Erase command will be disabled when OTP_LOCK is 1 WRSR command will ignore the input data and program LOCK_BIT to 1 User must clear the pr...

Page 68: ...g Table 8 Power Up Timing and Write Inhibit Threshold Symbol Parameter Min Max Unit tVSL 1 VCC min to CS low 10 µs tPUW 1 Time delay to Write instruction 1 10 ms VWI 1 Write Inhibit Voltage 1 2 5 V Note 1 The parameters are characterized only 2 VCC max is 3 6V and VCC min is 2 7V INITIAL DELIVERY STATE The device is delivered with the memory array erased all bits are set to 1 each byte contains FF...

Page 69: ... Current READ CLK 0 1 VCC 0 9 VCC at 75MHz DQ open 20 mA ICC4 Operating Current PP CS VCC 28 mA ICC5 Operating Current WRSR CS VCC 18 mA ICC6 Operating Current SE CS VCC 25 mA ICC7 Operating Current BE CS VCC 25 mA VIL Input Low Voltage 0 5 0 2 VCC V VIH Input High Voltage 0 7VCC VCC 0 4 V VOL Output Low Voltage IOL 1 6 mA 0 4 V VOH Output High Voltage IOH 100 µA VCC 0 2 V Table 10 AC Measurement ...

Page 70: ...ta In Setup Time 2 ns tCHDX tDH Data In Hold Time 5 ns tHLCH HOLD Low Setup Time relative to CLK 5 ns tHHCH HOLD High Setup Time relative to CLK 5 ns tCHHH HOLD Low Hold Time relative to CLK 5 ns tCHHL HOLD High Hold Time relative to CLK 5 ns tHLQZ 2 tHZ HOLD Low to High Z Output 6 ns tHHQX 2 tLZ HOLD High to Low Z Output 6 ns tCLQV tV Output Valid from CLK 8 ns tWHSL 3 Write Protect Setup Time be...

Page 71: ...bsequent versions 2004 Eon Silicon Solution Inc www eonssi com or modifications due to changes in technical specifications 26 EN25F16 Rev F Issue Date 2009 03 16 Figure 23 Serial Output Timing Figure 24 Input Timing Figure 25 Hold Timing ...

Page 72: ...nd Output Voltage with respect to ground 2 0 5 to 4 0 V Vcc 0 5 to 4 0 V Notes 1 No more than one output shorted at a time Duration of the short circuit should not be greater than one second 2 Minimum DC voltage on input or I O pins is 0 5 V During voltage transitions inputs may undershoot Vss to 1 0V for periods of up to 50ns and to 2 0 V for periods of up to 20ns See figure below Maximum DC volt...

Page 73: ... DATA RETENTION and ENDURANCE Parameter Description Test Conditions Min Unit 150 C 10 Years Data Retention Time 125 C 20 Years Erase Program Endurance 40 to 85 C 100k cycles Table 13 CAPACITANCE VCC 2 7 3 6V Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN 0 6 pF COUT Output Capacitance VOUT 0 8 pF Note Sampled only not 100 tested at TA 25 C and a frequency ...

Page 74: ...e Date 2009 03 16 PACKAGE MECHANICAL Figure 26 SOP 200 mil official name 208 mil MIN NOR MAX A 1 75 1 975 2 20 A1 0 05 0 15 0 25 A2 1 70 1 825 1 95 D 5 15 5 275 5 40 E 7 70 7 90 8 10 E1 5 15 5 275 5 40 e 1 27 b 0 35 0 425 0 50 L 0 5 0 65 0 80 θ 0 0 4 0 8 0 Note 1 Coplanarity 0 1 mm 2 Max allowable mold flash is 0 15 mm at the pkg ends 0 25 mm between leads SYMBOL DIMENSION IN MM ...

Page 75: ...ical specifications 30 EN25F16 Rev F Issue Date 2009 03 16 Figure 27 VDFN8 5x6mm Controlling dimensions are in millimeters mm DIMENSION IN MM SYMBOL MIN NOR MAX A 0 70 0 75 0 80 A1 0 00 0 02 0 04 A2 0 20 D 5 90 6 00 6 10 E 4 90 5 00 5 10 D2 3 30 3 40 3 50 E2 3 90 4 00 4 10 e 1 27 b 0 35 0 40 0 45 L 0 55 0 60 0 65 Note 1 Coplanarity 0 1 mm ...

Page 76: ...or modifications due to changes in technical specifications 31 EN25F16 Rev F Issue Date 2009 03 16 Figure 28 PDIP8 MIN NOR MAX A 0 210 A1 0 015 A2 0 125 0 130 0 135 D 0 355 0 365 0 400 E 0 300 0 310 0 320 E1 0 245 0 250 0 255 L 0 115 0 130 0 150 eB 0 310 0 350 0 375 Θ0 0 7 15 SYMBOL DIMENSION IN INCH ...

Page 77: ...s 32 EN25F16 Rev F Issue Date 2009 03 16 ORDERING INFORMATION EN25F16 100 H I P PACKAGING CONTENT Blank Conventional P RoHS compliant TEMPERATURE RANGE I Industrial 40 C to 85 C PACKAGE H 8 pin 200mil SOP W 8 pin VDFN Q 8 pin PDIP SPEED 100 100 Mhz BASE PART NUMBER EN Eon Silicon Solution Inc 25F 3V Serial 4KByte Uniform Sector FLASH 16 16 Megabit 2048K x 8 ...

Page 78: ... modify active current typical from 5mA to 12mA on page 2 3 List the Note 4 for 90h command in Table 4 on page 12 4 Update Table 6 Status Register Bit Locations on page 13 5 Add Table 7 OTP Sector Address on page 23 6 Add Note Vcc max is 3 6V and Vcc min is 2 7V in Table 8 on page 24 7 Modify ICC3 from Q open to DQ open in Table 9 on page 25 8 Correct the typo tCLH to tCH tCLL to tCL tHHQZ to tHHQ...

Page 79: ...7 Revision 1 9 22 Oct 2003 Modify refresh period page 1 13 23 40 41 Revision 2 0 17 Dec 2003 Delete The write burst length is programmed using A9 Test mode use A7 A8 Vendor specific options use A9 A10 A11 and A12 BA0 Revision 2 1 21Jul 2004 Correct typing errorÆ Page18 tCCDÆtCDL Page22 Note4 Note6 Page23 Note8ÆNote6 Page29 Note3 Note4 Correct plot1 2 clock suspended during read Page17 Correct plot...

Page 80: ...on for BRSW Revision 2 9 08 Dec 2006 Add BGA type to ordering information Revision 3 0 16 Mar 2007 Delete the mark of BGA package in packing diemension Revision 3 1 31 Jul 2007 Modify Icc2N test condition CS VIH Î CS VIH Revision 3 2 09 Oct 2007 Modify tSHZ timing Revision 3 3 05 May 2008 Add Revision History Rename A13 A12 to BA0 BA1 Delete frequency vs AC parameter relationship table ...

Page 81: ... Dynamic RAM organized as 4 x 1 048 576 words by 16 bits Synchronous design allows precise cycle controls with the use of system clock I O transactions are possible on every clock cycle Range of operating frequencies programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications PIN ASSIGNMENT Top ...

Page 82: ...of the CLK with RAS low Enables row access precharge CAS Column Address Strobe Latches column address on the positive going edge of the CLK with CAS low Enables column access WE Write Enable Enables write operation and row precharge Latches data in starting from CAS WE active L U DQM Data Input Output Mask Makes data output Hi Z tSHZ after the clock and masks the output Blocks data input when L U ...

Page 83: ... CONDITION Recommended operating conditions Voltage referenced to VSS 0V TA 0 to 70 C PARAMETER SYMBOL MIN TYP MAX UNIT NOTE Supply voltage VDD VDDQ 3 0 3 3 3 6 V Input logic high voltage VIH 2 0 VDD 0 3 V 1 Input logic low voltage VIL 0 3 0 0 8 V 2 Output logic high voltage VOH 2 4 V IOH 2mA Output logic low voltage VOL 0 4 V IOL 2mA Input leakage current IIL 5 5 μ A 3 Output leakage current IOL ...

Page 84: ...andby Current in non power down mode ICC2NS CKE VIH min CLK VIL max tcc input signals are stable 10 mA ICC3P CKE VIL max tcc tcc min 10 Active Standby Current in power down mode ICC3PS CKE CLK VIL max tcc 10 mA ICC3N CKE VIH min CS VIH min tCC 15ns Input signals are changed one time during 2clks All other pins VDD 0 2V or 0 2V 30 mA Active Standby Current in non power down mode One Bank Active ICC...

Page 85: ...in 38 40 42 ns 1 Row active time tRAS max 100 us Operating tRC min 53 58 63 ns 1 Row cycle time Auto refresh tRFC min 55 60 70 ns 1 5 Last data in to col address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tCCD min 1 CLK 3 CAS latency 3 2 Number of valid Output data CAS latency 2 1 ea 4 Note 1 Th...

Page 86: ...tput data hold time CAS latency 2 tOH 2 0 2 5 2 5 ns 2 CLK high pulsh width tCH 2 5 2 5 2 5 ns 3 CLK low pulsh width tCL 2 5 2 5 2 5 ns 3 Input setup time tSS 1 5 1 5 1 5 ns 3 Input hold time tSH 1 1 1 ns 3 CLK to output in Low Z tSLZ 0 0 0 ns 2 CAS latency 3 4 5 5 5 6 CLK to output in Hi Z CAS latency 2 tSHZ 6 6 6 ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is lon...

Page 87: ... be issued only at all banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatical precharge without row precharge of command is meant by Auto Auto self refresh can be issued only at all banks idle state 4 BA0 BA1 Bank select addresses If both BA0 and BA1 are Low at read write row active and precharge bank ...

Page 88: ... 0 1 Reserved Reserved 0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved Full Page Length 256 POWER UP SEQUENCE 1 Apply power and start clock Attempt to maintain CKE H DQM H and the other pin are NOP condition at the inputs 2 Maintain stable power stable clock and NOP input condition for a minimum of 200us 3 Issue precharge commands for all banks o...

Page 89: ... 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 BURST SEQUENCE BURST LENGTH 8 Initial A2 A1 A0 Sequential Interleave 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 ...

Page 90: ...ICE DESELECT When RAS CAS and WE are high The SDRAM performs no operation NOP NOP does not initiate any new operation but is needed to complete operations which require more than single clock cycle like bank activate burst read auto refresh etc The device deselect is also a NOP and is entered by asserting CS high CS high disables the command decoder so that RAS CAS WE and all the address inputs ar...

Page 91: ...as initiated to keep the data output gapless The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank The burst stop command is valid at every page burst length BURST WRITE The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycle...

Page 92: ... auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode CKE is high in the previous cycle The time required to complete the auto refresh operation is specified by tRFC min The minimum number of clock cycles required can be calculated by driving tRFC with clock cycle time and them rounding up to the next higher integer The auto refresh...

Page 93: ...her commands Activate command CS RAS Low CAS WE High The M12L64164A has four banks each with 4 096 rows This command activates the bank selected by BA1 and BA0 BS and a row address selected by A0 through A11 This command corresponds to a conventional DRAM s RAS falling Precharge command CS RAS WE Low CAS High This command begins precharge operation of the bank selected by BA1 and BA0 BS When A10 i...

Page 94: ...command CS CAS Low RAS WE High Read data is available after CAS latency requirements have been met This command sets the burst start address given by the column address CBR auto refresh command CS RAS CAS Low WE CKE High This command is a request to begin the CBR refresh operation The refresh address is generated internally Before executing CBR refresh all banks must be precharged After this cycle...

Page 95: ... exits the self refresh mode During self refresh mode refresh interval and refresh operation are performed internally so there is no need for external control Before executing self refresh all banks must be precharged Burst stop command CS WE Low RAS CAS High This command terminates the current burst operation Burst stop is valid at every burst length No operation CS Low RAS CAS WE High This comma...

Page 96: ...e d b y D Q M C L K C M D D Q M D Q C L 2 D Q C L 3 C K E R D Q0 Q2 Q4 H i Z H i Z H i Z Q6 Q7 Q8 Q5 Q6 Q7 Q1 Q3 H i Z H i Z H i Z H i Z H i Z 1 W r i t e M a s k B L 4 2 R e a d M a s k B L 4 D Q M t o D at a i n M a s k 0 DQ M t o D at a ou t M a s k 2 3 D Q M w i t h c l c o k s u s p e n d e d F u l l P a g e R e a d N o t e 2 I n t er n a l C L K Q9 Q8 C L K CM D CK E I nt e rn al CL K DQ C L...

Page 97: ... 3 tCDL Last data in to new column address delay 1CLK C L K C M D A D D D Q CL 2 DQ C L 3 R D QB0 QB 2 Q A 0 CL K C M D A D D D Q WR DA 0 D B0 DB 1 RD A B QB 1 QB 3 Q B 0 QB 2 QA0 QB 3 QB 1 tC C D N o t e 2 W R tC C D N o t e 2 A B t C D L N o t e 3 WR RD t C C D N o t e 2 A B D A 0 D B 0 D B 1 t C D L N o t e 3 D A 0 DB 0 D B1 DQ C L 3 D Q CL 2 1 R e a d i n t e r r u p t e d b y R e a d B L 4 2 ...

Page 98: ...n 3 3 20 46 4 CAS Interrupt II Read Interrupted by Write DQM C L K i C M D D Q M D Q D 1 D 3 D 0 D 2 W R i i C M D D Q M D Q i i i C M D D Q M D Q i v C M D D Q M D Q D 1 D 3 D 0 D 2 R D W R R D W R D 1 D 3 D 0 D 2 D 1 D3 D 0 D 2 R D W R H i Z Q0 N o t e 1 H i Z H i Z H i Z a C L 2 B L 4 R D ...

Page 99: ...hibit invalid write DQM should be issued 3 This precharge command and burst write command should be of the same bank otherwise it is not precharge interrupt but only another bank precharge of four banks operation C L K C M D D Q M D Q D 0 D 1 D 2 W R N o t e 3 N o t e 2 M a s k e d b y D Q M D 3 C L K i C M D i i C M D i i i C M D i v C M D D Q M D Q M D Q M D Q M D Q D Q D Q D Q D 1 D 3 D 1 D 0 D...

Page 100: ...d bank can be issued from this point At burst read write with auto precharge CAS interrupt of the same another bank is illegal C L K C M D D Q D 0 D 1 D2 D 3 W R tR D L N o t e 1 C L K C M D C M D D Q C L 2 Q0 Q1 Q2 Q3 R D PR E D Q C L 3 Q0 Q1 Q2 Q3 P R E 1 N o r m a l W r i t e B L 4 2 N o r m a l R e a d B L 4 C L 2 PR E CL 3 N o t e 2 N o t e 2 CL K C M D D Q D0 D 1 D2 D3 W R CL K C M D D Q C L...

Page 101: ...re or earlier satisfying tRAS min delay with DQM 6 PRE All banks precharge if necessary MRS can be issued only at all banks precharge state CL K C M D DQ C L 2 D Q C L 3 C L K CM D DQ M DQ D 0 D1 D2 D 3 WR ST OP N o t e 1 Q0 Q1 Q0 Q1 RD STO P N o t e 2 1 W r i t e B u r s t S t o p B L 8 2 R e a d B u r s t S t o p B L 4 CL K C M D D Q C L 2 C L K CM D DQ M DQ D 0 D1 M a sk M a sk W R Q0 Q1 R D P ...

Page 102: ... During self refresh entry refresh interval and refresh operation are performed internally After self refresh entry self refresh mode is kept while CKE is low During self refresh entry all inputs expect CKE will be don t cared and outputs will be in Hi Z state For the time interval of tRFC from self refresh exit command any other command can not be accepted C L K C K E I n t er n a l C L K C M D R...

Page 103: ...olated 2 At MRS A210 001 At auto precharge tRAS should not be violated 4 At MRS A210 010 8 At MRS A210 011 Basic MODE Full Page At MRS A210 111 At the end of the burst length burst is warp around Random MODE Burst Stop tBDL 1 Valid DQ after burst stop is 1 2 for CAS latency 2 3 respectively Using burst stop command any burst length control is possible RAS Interrupt Interrupted by Precharge Before ...

Page 104: ...L H BA CA A10 AP Term burst New Read Determine AP L H L L BA CA A10 AP Term burst New Write Determine AP 3 L L H H BA RA ILLEGAL 2 L L H L BA A10 AP Term burst Precharge timing for Reads L L L X X X ILLEGAL H X X X X X NOP Continue Burst to End Æ Row Active L H H H X X NOP Continue Burst to End Æ Row Active L H H L X X Term burst Æ Row active Write L H L H BA CA A10 AP Term burst New Read Determin...

Page 105: ...e after tRFC L H H X X X NOP Æ Idle after tRFC Refreshing L H L X X X ILLEGAL L L H X X X ILLEGAL L L L X X X ILLEGAL H X X X X X NOP Æ Idle after 2clocks Mode L H H H X X NOP Æ Idle after 2clocks Register L H H L X X ILLEGAL Accessing L H L X X X ILLEGAL L L X X X X ILLEGAL Abbreviations RA Row Address BA Bank Address NOP No Operation Command CA Column Address AP Auto Precharge Note 1 All entries...

Page 106: ... Power Mode H H X X X X X Refer to Table1 H L H X X X X Enter Power Down 8 H L L H H H X Enter Power Down 8 H L L H H L X ILLEGAL All H L L H L X X ILLEGAL Banks H L L L H H RA Row Bank Active Idle H L L L H H X NOP H L L L L L X Enter Self Refresh 8 H L L L L L OP Code Mode Register Access L L X X X X X NOP Any State H H X X X X X Refer to Operations in Table 1 other than H L X X X X X Begin Cloc...

Page 107: ...ESMT M12L64164A Elite Semiconductor Memory Technology Inc Publication Date May 2008 Revision 3 3 29 46 Single Bit Read Write Read Cycle Same Page CAS Latency 3 Burst Length 1 ...

Page 108: ...e auto precharge leave A bank active at end of burst 0 1 Disable auto precharge leave B bank active at end of burst 1 0 Disable auto precharge leave C bank active at end of burst 0 1 1 Disable auto precharge leave D bank active at end of burst 0 0 Enable auto precharge precharge bank A at end of burst 0 1 Enable auto precharge precharge bank B at end of burst 1 0 Enable auto precharge precharge ba...

Page 109: ...7 18 19 C L O C K C K E C S R A S C A S A D D R W E D Q D Q M A 10 A P t R P K e y R A a B A 0 B A 1 R A a H i g h Z P r e c h a r g e A l l B a n k s A u t o R e f r e s h A u t o R e f r e s h M o d e R e g i s t e r S e t R o w A c t i v e A B a n k D o n t c a r e t R F C t R F C H i g h l e v e l i s n e c e s s a r y H i g h l e v e l i s n e c e s s a r y ...

Page 110: ...b 1 Q b 2 Q b 3 Q b 0 Q a 0 R a N o t e 2 R b C b 0 R a C a 0 C b H I G H tR C D tR D L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 R b N o t e 3 Qa 1 Q a 2 Q a 3 Q b 1 Q b 2 Q b 3 Q b 0 Q a 0 tR D L N o t e 3 Precharge A Bank Note 1 Minimum row cycle times is required to complete internal DRAM operation 2 Row precharge can interrupt burst on any cycle CAS Latency 1 number of valid output da...

Page 111: ... n t C a r e Q a 0 Q a 1 Q b 0 Q b 1 D d 0 D d 1 t C D L D c 1 D c 0 Q a 1 Q b 0 Q b 1 Q b 2 D c 1 D d 0 D d 1 D c 0 Q a 0 R a N o t e 2 C c C d R a C a C b N o t e 1 H I G H t R C D t R D L BA1 Note 1 To Write data before burst read ends DQM should be asserted three cycle prior to write command to avoid bus contention 2 Row precharge will interrupt writing Last data input tRDL before row precharg...

Page 112: ... h a r g e C B a n k P r e c h a r g e D B a n k D o n t C a r e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 C L O C K C K E C S R A S C A S A D D R W E C L 2 D Q M A 1 0 A P B A 0 B A 1 C L 3 R B b C A a R C c C B b R D d C C c C D d N o t e 1 N o t e 2 R A a RDd QBb0 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 QAa1 QAa0 QAa2 QBb1 QAa0 QAa1 QAa2 QBb0 QCc1 QCc2 QDd0 QDd2 QDd1 QBb1 QCc0 QBb2 RAa RBb R...

Page 113: ... a 1 D A a 0 D B b 0 D B b 1 D Bb 3 D D d 0 D D d 1 D A a 2 D Bb 2 D C c 0 D C c 1 R A a R B b R C c R D d D Aa 3 C D d 2 tC D L R o w A c t i v e A Bank R o w A c t i v e B B a n k W r i t e A B a n k W r i t e B B a n k R o w A c t i v e C B a n k W r i t e C B a n k P r e c h a r g e A l l B a n k s R o w A c t i v e D B a n k W r i t e D B a n k H I G H tR D L Note 1 To interrupt burst write b...

Page 114: ... n k D o n t C a r e Q A a 1 Q A a 2 Q A a 3 D d b 1 D D b 2 D D d 3 D D b 0 Q A a 0 R A a C B c R A a C A a Q A a 1 Q A a 2 Q A a3 D d b1 D D b 2 D D d 3 D D b 0 Q A a 0 W r i t e D B a n k H I G H R D b C D b R B c R B b R A c Q B c 0 Q B c 1 Q B c 2 Q B c 0 Q B c 1 Read A Bank Row Active D Bank Precharge A Bank Row Active B Bank tC D L N o t e 1 1 9 2 1 0 3 4 5 6 7 8 1 1 1 2 1 3 1 4 1 7 1 5 1 8...

Page 115: ... L 2 C L 3 Row Active A Bank Row Active D Bank Auto Precharge Start Point Read with Auto Precharge A Bank Auto Precharge Start Point D Bank D o n t C a r e Q A a1 Q A a 2 Q A a 3 D d b 1 D D b 2 D D d 3 D D b 0 QA a 0 R a C b R a C a R b R b Q A a 1 Q A a 2 Q A a 3 D d b 1 D D b 2 D D d 3 D D b 0 Q A a 0 Write with Auto Precharge D Bank H I G H BA0 BA1 Note 1 tCDL should be controlled to meet mini...

Page 116: ... A S A D D R W E D Q D Q M A 1 0 A P R a C a C b C c R a Q a 0 Q a 1 Q a 2 Q a 3 t S H Z Q b 1 Q b 0 t S H Z D c 0 D c 2 N o t e 1 R o w A c t i v e R e a d C l o c k S u p e n s i o n R e a d R e a d D Q M W r i t e W r i t e D Q M C l o ck S u s p e n s io n W r i t e D Q M D o n t C a r e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 BA0 BA1 Note 1 DQM is needed to prevent bus contention ...

Page 117: ... e a d A B a n k B u r s t S t o p R e a d A B a n k D o n t C a r e H I G H C L 2 C L 3 Q A a2 Q A a 3 QA a 4 Q A b3 Q A b 4 Q A b5 Q A a 0 Q A a 1 Q A b 1 Q A b 0 Q A b 2 QA a 2 QA a 3 Q A a 4 QA b 3 Q A b 4 Q A b 5 1 1 2 2 P r e c h a r g e A B a n k BA0 BA1 Note 1 About the valid DQs after burst stop it is same as the case of RAS interrupt Both cases are illustrated above timing diagram See th...

Page 118: ... n t C a r e H I G H D A a 2 D A a 3 D Aa 4 D A b 3 D Ab 4 D A b 5 P r e c h a r g e A B a n k tB D L tR D L N o t e 1 1 9 2 1 0 3 4 5 6 7 8 11 12 13 14 17 15 18 16 19 0 Note 1 Data in at the cycle of interrupted by precharge can not be written into the corresponding memory cell It is defined by AC parameter of tRDL DQM at write interrupted by precharge command is needed to prevent invalid write D...

Page 119: ... o t e 3 N o t e 2 N o t e 1 tS S tS S t S S Q a 0 Q a 1 Q a 2 tS H Z P r e c h a r g e P o we r D o w n En tr y P r e c h a r g e P o we r D o w n E x i t R o w A c t i v e A c t i v e P o w e r d o w n E n t r y R e a d 0 1 2 3 4 5 6 7 8 9 1 0 11 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 B A 0 R a R a C a Note 1 Both banks should be in idle state prior to entering precharge power down mode 2 CKE should be...

Page 120: ...te TO ENTER SELF REFRESH MODE 1 CS RAS CAS with CKE should be low at the same clock cycle 2 After 1 clock cycle all the inputs including the system clock can be don t care except for CKE 3 The device remains in self refresh mode as long as CKE stays Low cf Once the device enters self refresh mode minimum tRAS is required before exit from self refresh TO EXIT SELF REFRESH MODE 4 System clock restar...

Page 121: ...CLE Note 1 CS RAS CAS WE activation at the same clock cycle with address key will set internal mode register 2 Minimum 2 clock cycles should be met before new RAS activation 3 Please refer to Mode Register Set table C L O C K C K E C S R A S C A S A D D R W E D Q D Q M D o n t C a r e H I G H 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 1 0 H I G H Ke y R a H I Z H I Z N o t e 2 N o t e 1 N o t e 3 tR F C M ...

Page 122: ... 006 A2 0 95 1 00 1 05 0 037 0 039 0 041 b 0 25 0 45 0 010 0 018 b1 0 25 0 35 0 40 0 010 0 014 0 016 c 0 12 0 21 0 005 0 008 c1 0 10 0 127 0 16 0 004 0 005 0 006 D 22 22 BSC 0 875 BSC E 11 76 BSC 0 463 BSC E1 10 16 BSC 0 400 BSC L 0 40 0 50 0 60 0 016 0 020 0 024 L1 0 80 REF 0 031 REF e 0 80 BSC 0 031 BSC Θ 0 10 0 10 O L DETAIL A SECTION B B B B 0 10 C D E E1 e PLANE SEATING 1 L 1 27 28 54 A2 A H ...

Page 123: ...8x8 mm Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max A 1 00 0 039 A1 0 20 0 25 0 30 0 008 0 010 0 012 A2 0 61 0 66 0 71 0 024 0 026 0 028 Φb 0 30 0 35 0 40 0 012 0 014 0 016 D 7 90 8 00 8 10 0 311 0 315 0 319 E 7 90 8 00 8 10 0 311 0 315 0 319 D1 6 40 0 252 E1 6 40 0 252 e 0 80 0 031 Controlling dimension Millimeter ...

Page 124: ...r other intellectual property rights of third parties which may result from its use No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of ESMT or others Any semiconductor devices may have inherently a certain rate of failure To minimize risks associated with customer s application adequate design and operating safeguards aga...

Page 125: ...2 Reference Information 2 1 Component Descriptions 2 1 1 DVD SONY HM 313 Connector Pin Definition 5 PUH ...

Page 126: ...T 5 55 6 is 3 135V Parameter Symbol Rating Unit Ambient Temperature TA 0 70 C Storage Temperature TSTG 55 125 C Voltage on Any Pin relative to VSS VIN VOUT 1 0 4 6 V Voltage on VDD relative to VSS VDD VDDQ 1 0 4 6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W Soldering Temperature Time TSOLDER 260 10 C Sec Parameter Symbol Min Typ Max Unit Note Power Supply Voltage VDD VDDQ 3 0...

Page 127: ... Relative humidity 5 90 TV System PAL NTSC Frequency Reponse THD NOISE 60dB 1KHz S N A weight 70dB 1KHz FM band Range 64MHz 108MHz Power output Max 15WX5 30W Power consumption 105W Disc output Tuner Frequency response AM frequency Range 1 5dB 20Hz 20KHz Dynamic Range 80dB 1KHz 1 5dB 20Hz 20KHz ...

Page 128: ...DIATEK ISO9660 LEVEL1 MODE1 not JOILET 3 Put the recorded disc into the DVD player on the TV will show upgrade after loading Press PLAY button the player will automatically upgrade 4 Do not shut down the player during upgrade it will restart automatically after upgrade 5 Upgrade finish How to change the region code 1 Power on the machine and press OPEN button to push the tray out 2 Press 1 3 6 9 b...

Page 129: ...yer About 4hrs Double side Single layer DVD AUDIO VIDEO 12CM About 8hrs Double side double layer CD DA AUDIO 12CM About 74 minutes MP3 AUDIO 12CM About 300 minutes To handle clean and protect discs Do not touch the playing side of a disc Do not stick any paper or glue strip on a disc How to clean discs Finger prints and dust on surface can affect the sound and picture quality Clean discs regularly...

Page 130: ...a compatible disc Check the disc format and its colour system T do he disc is placed upside wn Load a compatible disc Check the disc format and its colour system The disc not put in the tray correctly Check disc is put in correctly Disc is dirty Clean the disc Player setting are incorrect Change the setting via the setup menu The player does not work Parental lock is in effect Disable this functio...

Page 131: ......

Page 132: ... TROUT VR_DVD ASPDIF ADVCM AKIN1 TRCLOSE TRIN UP1_6 UP1_7 94 95 VSCK VSDA MS_CLK GPIO20 GPIO21 107 108 97 106 AUDIO_MUTE GPO14 GPIO19 SCART1 SCART2 VSTB MT1389J General GPIO List Gxyz_CLK MS_BS MS_D0 SD_CLK SD_CMD SD_D0 LIMIT Gxyz_DA1 Gxyz_DA2 VSYNC HSYNC Gxyz_LOAD RXD GPIO3 STBY TROPEN IOA GPIO30 GPIO31 GPIO10 GPIO33 GPI36 124 TXD AKIN2 RESET Circuit C1 close to 89J pin Standby Power Control Powe...

Page 133: ...ndby IR Power Key JP1 2x2 JP1 2x2 1 2 3 4 R15 0 R15 0 CB10 0 1uF CB10 0 1uF JP2 2x2 JP2 2x2 1 2 3 4 R22 5 1k 1 R22 5 1k 1 C14 0 1uF C14 0 1uF D1 BAT54C D1 BAT54C 1 3 2 R13 560 R13 560 C11 4 7uF C11 4 7uF C21 0 1uF C21 0 1uF CB7 0 1uF CB7 0 1uF CB16 0 1uF CB16 0 1uF MT1389J LQFP 128 V1 0 No EPAD U1 MT1389J LQFP128 SMD D14X14 MT1389J LQFP 128 V1 0 No EPAD U1 MT1389J LQFP128 SMD D14X14 AVDD12_2 5 AVD...

Page 134: ... SDR_DRAM Dual Layout Serial Flash POWER Motor Driver Vref Vref 3 3V Ra Rb Ra Rb 0 NC 20K 12K 1 2V output AM5888 AT5669 U5 EN25F16 U5 EN25F16 CE 1 SO 2 WP 3 VSS 4 SI 5 SCK 6 HOLD 7 VDD 8 D3 IN4001 DIP D3 IN4001 DIP CE16 100uF 6 3v CE16 100uF 6 3v J5 5x1 W HOUSING J5 5x1 W HOUSING 1 2 3 4 5 CB20 0 1uF CB20 0 1uF CB18 0 1uF CB18 0 1uF C23 0 1uF C23 0 1uF U3 ESMT M12L64164A U3 ESMT M12L64164A VCC 1 D...

Page 135: ...1 1000pF C31 1000pF R48 5 1k R48 5 1k R88 1k R88 1k C37 0 1uF C37 0 1uF R64 1k R64 1k R69 10 R69 10 R91 47k R91 47k C42 3300pF C42 3300pF J6 4x1 W HOUSING DIP4 W H P2 0 J6 4x1 W HOUSING DIP4 W H P2 0 1 2 3 4 C25 100pF C25 100pF C34 100pF C34 100pF U7A NJM4558 OPA U7A NJM4558 OPA 3 2 1 8 4 R72 31k R72 31k R46 31k R46 31k CE30 10uF 16v CE30 10uF 16v CE21 10uF 16v CE21 10uF 16v R53 100k R53 100k CE32...

Page 136: ...e to RCA connector Close to RCA connector Close to RCA connector Improve Video Performance Support Scart CVBS output at the same time 1 8uH 1 8uH Close to RCA connector 1 8uH L15 0R L15 0R C48 100pF NC C48 100pF NC R123 75 1 R123 75 1 R116 75 1 R116 75 1 D9 DIODE SMD BAV99 D9 DIODE SMD BAV99 1 3 2 C52 100pF NC C52 100pF NC C50 100pF NC C50 100pF NC R108 3 3k R108 3 3k Q21 2N3904 Q21 2N3904 1 3 2 R...

Page 137: ... 1 1 Custom 6 7 Thursday August 13 2009 COMMON1389J_HD850_AM5888_STBY MediaTek Confidential guibing luo Sam xie Gxyz I F Gxyz I F USB I F MCR I F POWER OFF PAGE CONNECTION close to USB connector USB I F MCR I F R128 0R R128 0R J9 6x1 W HOUSING J9 6x1 W HOUSING 1 2 3 4 5 6 Q26 2N3904 Q26 2N3904 1 3 2 CE39 47uF 10v CE39 47uF 10v CE40 100uF 16v CE40 100uF 16v R127 0 R127 0 R131 3 3k R131 3 3k CE38 47...

Page 138: ...t of MediaTek ShenZhen Inc Drawn Checked Power Flow 1 1 A 7 7 Thursday August 13 2009 COMMON1389J_HD850_AM5888_STBY MediaTek Confidential guibing luo Sam xie Title Size Document Number Rev Date Sheet of MediaTek ShenZhen Inc Drawn Checked Power Flow 1 1 A 7 7 Thursday August 13 2009 COMMON1389J_HD850_AM5888_STBY MediaTek Confidential guibing luo Sam xie Power Board Switch Switch VFD 3 3V 1 2V Moto...

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Page 142: ...5 U901 SM1628 1 1 2 2 R28 R0603P 10K R30 R0603P 10K SW10 SW_KEY E CUSTOMERVESTELPORTABLE1000ÔÝÊ VESTEL_PORTABLE1000_89E_QSI086T_V2 DSN SW8 SW_KEY E CUSTOMERVESTELPORTABLE1000ÔÝÊ VESTEL_PORTABLE1000_89E_QSI086T_V2 DSN SW9 SW_KEY E CUSTOMERVESTELPORTABLE1000ÔÝÊ VESTEL_PORTABLE1000_89E_QSI086T_V2 DSN SW7 SW_KEY E CUSTOMERVESTELPORTABLE1000ÔÝÊ VESTEL_PORTABLE1000_89E_QSI086T_V2 DSN 1 2 3 4 5 6 7 8 CN1...

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Page 144: ...R107 1 2 D504 DIODE_3 1N5399 1 1 2 2 3 3 4 4 U502 817 817 1 2 D501 DIODE_6 1N5399 1 2 R507 R_0 1K 1 2 D511 D_10 HER303 2 3 4 6 7 10 11 12 13 14 15 16 17 18 1 3 5 8 9 EC2828 T_1 T1 1 2 L502 INDUCTOR_DIPA FB 1 2 TC2 CAP_0A 10U50V 1 1 2 2 3 3 4 4 5 5 6 6 U7 FSDM0565 FSDM0565 1 1 2 2 CN11 2P3 96 2P3 96 1 1 2 2 CN12 2P3 96 2P3 96 1 1 2 2 FUSE2 FUSE 250V 2A 1 1 2 2 D4 D_11 HER303 1 1 2 2 3 3 4 4 5 5 6 6...

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