General Standards Corporation PCI-SIO4, User Manual

Page: 10 / 66

PCI-SIO4 User Manual
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
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2.3.19.2 High: (LOC 0xn25)....................................................................................................................................... 34
2.3.20 Receive Interrupt Control Register (RICR) ..................................................................................................... 34
2.3.20.1 Low: (LOC 0xn26) ....................................................................................................................................... 34
2.3.20.2 High: (LOC 0xn27)....................................................................................................................................... 34
2.3.21 Receive Sync Register (RSR) ............................................................................................................................ 34
2.3.21.1 Low: (LOC 0xn28) ....................................................................................................................................... 35
2.3.21.2 High: (LOC 0xn29)....................................................................................................................................... 35
2.3.22 Receive Count Limit Register (RCLR) ............................................................................................................. 35
2.3.22.1 Low: (LOC 0xn2A) ...................................................................................................................................... 35
2.3.22.2 High: (LOC 0xn2B) ...................................................................................................................................... 35
2.3.23 Receive Character Count Register (RCCR) ..................................................................................................... 35
2.3.23.1 Low: (LOC 0xn2C)....................................................................................................................................... 35
2.3.23.2 High: (LOC 0xn2D)...................................................................................................................................... 35
2.3.24 Time Constant 0 Register (TC0R) .................................................................................................................... 35
2.3.24.1 Low: (LOC 0xn2E)....................................................................................................................................... 35
2.3.24.2 High: (LOC 0xn2F)....................................................................................................................................... 35
2.3.25 Transmit Mode Register (TMR) ....................................................................................................................... 35
2.3.25.1 Low: (LOC 0xn32) ....................................................................................................................................... 35
2.3.25.2 High: (LOC 0xn33)....................................................................................................................................... 36
2.3.26 Transmit Command/Status Register (TCSR) .................................................................................................. 36
2.3.26.1 Low: (LOC 0xn34) ....................................................................................................................................... 36
2.3.26.2 High: (LOC 0xn35)....................................................................................................................................... 36
2.3.27 Transmit Interrupt Control Register (TICR) ................................................................................................... 37
2.3.27.1 Low: (LOC 0xn36) ....................................................................................................................................... 37
2.3.27.2 High: (LOC 0xn37)....................................................................................................................................... 37
2.3.28 Transmit Sync Register (TSR) ......................................................................................................................... 37
2.3.28.1 Low: (LOC 0xn38) ....................................................................................................................................... 37
2.3.28.2 High: (LOC 0xn39)....................................................................................................................................... 37
2.3.29 Transmit Count Limit Register (TCLR) ............................................................................................................ 38
2.3.29.1 Low: (LOC 0xn3A) ...................................................................................................................................... 38
2.3.29.2 High: (LOC 0xn3B) ...................................................................................................................................... 38
2.3.30 Transmit Character Count Register (TCCR) ................................................................................................... 38
2.3.30.1 Low: (LOC 0xn3C)....................................................................................................................................... 38
2.3.30.2 High: (LOC 0xn3D)...................................................................................................................................... 38
2.3.31 Time Constant 1 Register (TC1R) ................................................................................................................... 38
2.3.31.1 Low: (LOC 0xn3E)....................................................................................................................................... 38
2.3.31.2 High: (LOC 0xn3F)....................................................................................................................................... 38
CHAPTER 3: PCI INTERFACE
...................................................................................................................................39
3.0 PCI INTERFACE REGISTERS .................................................................................................................................... 39
3.1 PCI CONFIGURATION REGISTERS......................................................................................................................... 39
TABLE 3.1-1 PCI CONFIGURATION REGISTERS ........................................................................................ 39
3.1.1 PCI Configuration ID Register: (Offset 0x00, Reset 0x908010B5) ................................................................ 40
3.1.2 PCI ........................................................................................................................................................................ 40
3.1.3 PCI Status Register: (Offset 0x06, Reset 0x0280) ........................................................................................... 40
3.1.4 PCI Revision ID Register : (Offset 0x08) ......................................................................................................... 41
3.1.5 PCI Class Code Register: (Offset 0x09-0B, Reset=0x068000) ....................................................................... 41
3.1.6 PCI Cache Line Size Register: (Offset 0x0C, Reset 0x00) .............................................................................. 41
3.1.7 PCI Latency Timer Register : (Offset 0x0D, Reset 0x00) ............................................................................... 41
3.1.8 PCI Header Type Register: (Offset 0x0E, Reset 0x00) ................................................................................... 41
3.1.9 PCI Base Address Register for Memory Access to Local/Runtime/DMA Registers