General Standards Corporation PCI-SIO4, User Manual

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PCI-SIO4 User Manual
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
14
D15 Channel 1 Rx FIFO Full (TRUE == 0)
The FIFO status flags are active low indicators of the current FIFO status. These flags are
continuously being updated every 33ns. A value of ‘0’ indicates that the current status is true and
a value of ‘1’ indicates that it is not true. There are only 5 valid combinations for each nibble
(D8..D11 or D12..D15). These combinations are as follows:
0xC 1100 Almost Empty and Empty
0xD 1101 Almost Empty but not Empty
0xF 1111 In between Almost Empty and Almost Full
0xB 1011 Almost Full but not full
0x3 0011 Almost Full and Full
2.1.8 C
HANNEL
2 T
X
A
LMOST
: (LOC 0
X
20)
D7..0 Channel 2 Tx Almost Data
The data in this register is used for programming the Almost Flags of the Tx FIFOs for
this channel.
D0..15 Used for the Almost Empty Flag
D16..31 Used for the Almost Full Flag
2.1.9 C
HANNEL
2 R
X
A
LMOST
: (LOC 0
X
24)
D0..7 Channel 2 Rx Almost Data
The data in this register is used for programming the Almost Flags of the Tx FIFOs for
this channel.
D0..15 Used for the Almost Empty Flag
D16..31 Used for the Almost Full Flag
2.1.10 C
HANNEL
2 FIFO: (LOC 0
X
28)
D0..7 Channel 2 FIFO Data
The FIFOs are setup in a way that the Rx FIFO and the Tx FIFO are located at
the same address. A write to this address will be directed toward the Tx FIFO,
and a read from this address will be directed toward the Rx FIFO.
2.1.11 C
HANNEL
2 C
ONTROL
/S
TATUS
: (LOC 0
X
2C)
D0 Reset Channel 2 Tx FIFO (Pulsed)
Writing a ‘1’ to this bit will cause the channel 2 Tx FIFOs to be reset. If the
channel 2 Tx Almost register is not a value of 0x00000000 then this will also
cause the channel 2 Tx FIFOs almost flags to be programmed. After setting this
bit to a ‘1’, it is the software’s responsibility to delay approximately 10ms before
accessing the local side of the board again. This bit is a self-timed pulse;
therefore, it is not necessary for software to return to clear this bit, it will clear
itself.
D1 Reset Channel 2 Rx FIFO (Pulsed)
Writing a ‘1’ to this bit will cause the channel 2 Rx FIFOs to be reset. If the
channel 2 Rx Almost register is not a value of 0x00000000 then this will also
cause the channel 2 Rx FIFOs almost flags to be programmed. After setting this
bit to a ‘1’, it is the software’s responsibility to delay approximately 10ms before