General Standards Corporation PCI-SIO4, User Manual

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PCI-SIO4 User Manual
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
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(Offset 0x010, Reset 0x00000000) ...................................................................................................................... 42
3.1.10 PCI Base Address Register for I/O Access to Local/Runtime/DMA Registers
(Offset 0x14, Reset 0x00000001) ........................................................................................................................ 42
3.1.11 PCI Base Address Regis ter for Memory Access to Local Address Space 0
(Offset 0x18, Reset 0x00000000) ........................................................................................................................ 42
3.1.12 PCI Subsystem Device/Vendor ID Register: (Offset 0x2C, Reset 0x908010B5) ......................................... 42
3.1.13 PCI Interrupt Line Register: (Offset 0x3C, Reset 0x00) .................................................................................. 43
3.1.14 PCI Interrupt Pin Register : (Offset 0x3D, Reset 0x01) .................................................................................. 43
3.1.15 PCI Min_Gnt Register : (Offset 0x3E, Reset 0x00) ......................................................................................... 43
3.1.16 PCI Max_Lat Register : (Offset 0x3F, Reset 0x00) .......................................................................................... 43
3.2 Local Configuration Registers.................................................................................................................................... 44
TABLE 3.2-1 LOCAL CONFIGURATION REGISTERS .................................................................................. 44
3.2.1 Local Address Space 0 Range Register for PCI to Local Bus
(PCI 0x00, Reset 0xFFFFF000) ........................................................................................................................... 44
3.2.2 Mode/Arbitration Register : (PCI 0x08) ........................................................................................................... 45
3.2.3 Big/Little Endian Descriptor Register : (PCI 0x0C) ........................................................................................ 45
3.2.4 Local Address Space 0/Expansion ROM Bus Region Descriptor Register
(PCI 0x18, Reset 0x40030143) ............................................................................................................................ 45
3.3 Runtime Registers ........................................................................................................................................................ 46
TABLE 3.3-1 RUNTIME REGISTERS ................................................................................................................. 46
3.3.1 Interrupt Control /Status : (PCI 0x68, Reset 0x00000000) .............................................................................. 46
3.3.2 Serial EEPROM Control, PCI Command Codes, User I/O Control, Init Control Register: (PCI ...............
0x6C, Reset 0x0x001767E ) .................................................................................................................................. 47
3.3.3 PCI Permanent Configuration ID Register : (PCI 0x70, Reset 0x10B59080) ................................................ 47
3.3.4 PCI Permanent Revision ID Register: (PCI 0x74) ........................................................................................... 47
3.4 Local DMA Registers .................................................................................................................................................. 48
TABLE 3.4-1 DMA REGISTERS .......................................................................................................................... 49
3.4.1 DMA Channel 0 Mode Register : (PCI 0x80) .................................................................................................. 48
3.4.2 DMA Channel 0 PCI Address Register : (PCI 0x84) ...................................................................................... 49
3.4.3 DMA Channel 0 Local Address Register : (PCI 0x88) .................................................................................. 49
3.4.4 DMA Channel 0 Transfer Size (Bytes) Register: (PCI 0x8C) ........................................................................ 49
3.4.5 DMA Channel 0 Descriptor Pointer Register : (PCI 0x90) ............................................................................ 49
3.4.6 DMA CHANNEL 0 Command/Status Register : (PCI 0xA8) ........................................................................ 49
3.4.7 DMA Arbitration Register : (PCI 0xAC) ......................................................................................................... 50
3.4.8 DMA Threshold Register: (PCI 0xB0) ............................................................................................................. 50
3.5 Messaging Queue Registers ...................................................................................................................................... 50
CHAPTER 4: PROGRAMMING
..............................................................................................................................51
4.0 Introduction .................................................................................................................................................................. 51
4.1 Resets ............................................................................................................................................................................. 51
4.2 FIFO Almost Flags....................................................................................................................................................... 51
4.3 PCI DMA....................................................................................................................................................................... 52
4.4 Zilog Z16C30 DMA...................................................................................................................................................... 52
4.5 Interrupts ....................................................................................................................................................................... 52
CHAPTER 5: HARDWARE CONFIGURATION
............................................................................................53
5.0 The On-board Master and Transmit/Receive Clocks ............................................................................................. 53
5.1 Eeprom Jumper(J12) ..................................................................................................................................................... 53
5.2 Cable Interface Connections ...................................................................................................................................... 53
TABLE 5.2-1 USER CABLE PIN-OUT ................................................................................................................. 53
5.3 Board Layout ................................................................................................................................................................ 54
FIGURE 5.4-1 BOARD LAYOUT .......................................................................................................................... 54