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PCI-SIO4 User Manual

General Standards Corporation

8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787

40

Note:

The Local Base Address for the PCI Configuration registers in Local Address Space is 0xC0000000.
However, there should be no need for the user to access the PCI Configuration registers through Local
Address Space.

3.1.1

PCI

C

ONFIGURATION

ID

R

EGISTER

:

(O

FFSET

0

X

00,

R

ESET

0

X

908010B5)

D15:0

V

ENDOR

ID

––

0

X

10B5

=

PLX

T

ECHNOLOGY

D31:16

D

EVICE

ID

––

0

X

9080

=

PCI9080

3.1.2

PCI

D0

I/O

S

PACE

A ‘1’ allows the device to respond to I/O space accesses.

D1

Memory Space

A ‘1’ allows the device to respond to memory space accesses.

D2

PCI Master Enable.

A ‘1’ allows the device to behave as a PCI bus master.

Note:

This bit must be set for the PCI 9080 to perform DMA cycles.

D3

Special Cycle. (

Not Supported

.)

D4

Memory Write/Invalidate.

A ‘1’ enables memory write/invalidate.

D5

VGA Palette Snoop. (

Not Supported

.)

D6

Parity Error Response

A ‘0’ indicates that a parity error is ignored and operation continues.

A ‘1’ indicates that parity checking is enabled.

D7

Wait Cycle Control. Controls whether the device does address/data stepping.

A ‘0’ indicates the device never does address/data stepping.

Note:

Hardcoded to 0.

D8

SERR# Enable

A ‘1’ allows the device to drive the SERR# line.

D9

Fast Back-to-Back Enable. Indicates what type of fast back-to-back transfers a Master can
perform on the bus.
A ‘1’ indicates fast back-to-back transfers can occur to any agent on the bus.
A ‘0’ indicates fast back-to-back transfers can only occur to the same agent as the
previous cycle.

D15:10

Reserved

3.1.3

PCI

S

TATUS

R

EGISTER

:

(O

FFSET

0

X

06,

R

ESET

0

X

0280)

D5:0

Reserved

D6

User Definable Features Supported
A ‘1’ indicates UDF are supported.

Note:

User Definable Features are Not Implemented.

D7

Fast Back-to-Back Capable.
A ‘1’ indicates the adapter can accept fast back-to-back transactions.

D8

Master Data Parity Error Detected

A ‘1 indicates the following three conditions are met:

1. PCI9080 asserted PERR# itself or observed PERR# asserted.
2. PCI9080 was bus master for the operation in which the error occurred.
3. Parity Error Response bit in the Command Register is set.

Writing a ‘1’ to this bit clears the bit.

D10:9

DEVSEL Timing. Indicates timing for DEVSEL# assertion.
A value of ‘01’ indicates a medium decode.

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Summary of Contents for PCI-SIO4

Page 1: ...PCI SIO4 User Manual General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL www generalstandards com E mail techsupport generalstandards com...

Page 2: ......

Page 3: ...ecember 1 1997 edited bit map and bit descriptions edited section numbering and edited table of contents 4 December 2 1997 edited Chapter 3 hardware configurations 5 April 17 1998 Updated bit map 6 Ap...

Page 4: ...rds Corporation does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent right of any rights of other...

Page 5: ......

Page 6: ...oposed standard Wayne Fisher PMC Chair 2001 Logic Drive San Jose CA 95124 3456 USA Ph 408 369 6250 Fax 408 371 3382 Em wfisher fci com Dave Moore PMC Draft Editor Digital Equipment Corporation 146 Mai...

Page 7: ......

Page 8: ...0x24 14 2 1 10 Channel 2 FIFO LOC 0x28 14 2 1 11 Channel 2 Control Status LOC 0x2C 14 2 1 12 Channel 3 Tx Almost LOC 0x30 16 2 1 13 Channel 3 Rx Almost LOC 0x34 16 2 1 14 Channel 3 FIFO LOC 0x38 16 2...

Page 9: ...R 27 2 3 9 1 Low LOC 0xn10 27 2 3 9 2 High LOC 0xn11 27 2 3 10 Hardware Configuration Register HCR 28 2 3 10 1 Low LOC 0xn12 28 2 3 10 2 High LOC 0xn13 28 2 3 11 Interrupt Vector Register IVR 28 2 3 1...

Page 10: ...27 1 Low LOC 0xn36 37 2 3 27 2 High LOC 0xn37 37 2 3 28 Transmit Sync Register TSR 37 2 3 28 1 Low LOC 0xn38 37 2 3 28 2 High LOC 0xn39 37 2 3 29 Transmit Count Limit Register TCLR 38 2 3 29 1 Low LO...

Page 11: ...143 45 3 3 Runtime Registers 46 TABLE 3 3 1 RUNTIME REGISTERS 46 3 3 1 Interrupt Control Status PCI 0x68 Reset 0x00000000 46 3 3 2 Serial EEPROM Control PCI Command Codes User I O Control Init Control...

Page 12: ...The Zilog Clock Select Jumpers J3 J4 J7 J8 54 FIGURE 5 4 2 CLOCK JUMPERS ROUTING 55 FIGURE 5 4 3 DATA ROUTING 55 FIGURE 5 4 4 CTS DCD ROUTING 56 CHAPTER 6 ORDERING OPTIONS 57 6 0 Ordering Information...

Page 13: ...Interface Interrupt functionality FIFOs are provided for data transmit and for data receive to increase the size of the receive buffers User interface signals connections are provided via connectors o...

Page 14: ...data from the Z16C30 or have the data buffered into the main Rx FIFOs and retrieved by the software at a later time depending on how the Z16C30 has been initialized 1 6 DATA TRANSMISSION Data is place...

Page 15: ...General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 8 Tx FIFO almost empty Rx FIFO almost full Exited Hunt IdleRcvd Break Abort RxBound Abort ParityError RxOver...

Page 16: ...Empty 0x2C D32 RW Channel 2 Control Status 0xXXXXCCXX 0x30 D32 RW Channel 3 Tx Almost 0xXXXXXXXX 0x34 D32 RW Channel 3 Rx Almost 0xXXXXXXXX 0x38 D32 RW Channel 3 FIFO Empty 0x3C D32 RW Channel 3 Cont...

Page 17: ...al Channel 3 Rx FIFO Almost Full Hold until Serial Channel 3 Rx FIFO Almost Empty 1 0 1 Request DMA on Serial Channel 3 Tx FIFO Almost Empty Hold until Serial Channel 3 Rx FIFO Almost Empty 0 1 1 Requ...

Page 18: ...signal on the cable to go from a tri state condition to a loaded condition D4 Channel 2 Enable Drive Upper Clk Writing a 1 to this bit will turn on the transmitter for the Channel 2 Tx Clk on the uppe...

Page 19: ...annel 4 Enable Receive Upper Clk Writing a 1 to this bit will turn on the receiver for the Channel 4 Rx clock on the upper portion of the cable This will cause this signal on the cable to go from a tr...

Page 20: ...tion of the cable will drive the Cable Writing a 1 to this bit will turn on the transmitters for the Channel 1 lower portion of the cable The signals that are turned on are the Channel 1 TxD and Chann...

Page 21: ...channel D0 15 Used for the Almost Empty Flag D16 31 Used for the Almost Full Flag 2 1 10 CHANNEL 2 FIFO LOC 0X28 D0 7 Channel 2 FIFO Data The FIFOs are setup in a way that the Rx FIFO and the Tx FIFO...

Page 22: ...aded condition D5 Enable the Channel 2 Receivers for the Lower portion of the cable will load the cable Writing a 1 to this bit will turn on the receivers for the Channel 2 lower portion of the cable...

Page 23: ...it is the software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to return t...

Page 24: ...eturn to clear this bit it will clear itself Note that after power up and after any reset to this component the next access to channel 3 or channel 4 USC must be a write of 0x00 to offset 0x00 of chan...

Page 25: ...ore it is not necessary for software to return to clear this bit it will clear itself D2 Enable the Channel 4 Transmitters for the Upper portion of the cable will drive the cable Writing a 1 to this b...

Page 26: ...0xC 1100 Almost Empty and Empty 0xD 1101 Almost Empty but not Empty 0xF 1111 In between Almost Empty and Almost Full 0xB 1011 Almost Full but not full 0x3 0011 Almost Full and Full 2 1 20 CHANNEL 1 SY...

Page 27: ...Enable Channel 3 Interrupt on Rx FIFO Almost Full D11 Enable Channel 3 Interrupt on USC Request Interrupt D12 Enable Channel 4 Interrupt on Sync Detected D13 Enable Channel 4 Interrupt on Tx FIFO Almo...

Page 28: ...ntrol register is a 1 then the source has performed a PCI interrupt and has latched itself Writing a 1 to the respective bit in the interrupt status register clears the interrupt status bit A second i...

Page 29: ...resses n stands for Channel Number 2 3 1 CHANNEL COMMAND ADDRESS REGISTER CCAR Same format for Channels 0 3 USC Control Registers 2 3 1 1 Low LOC 0xn00 D0 WO Upper Lower Byte Select D1 D5 WO Address 4...

Page 30: ...Reserved 11101 Reserved 11110 Reserved 11111 Reserved Selected upon reset 2 3 2 CHANNEL MODE REGISTER CMR 2 3 2 1 Low LOC 0xn02 D0 D3 WO Receiver Mode encoded as follows 0000 Asynchronous 0001 Extern...

Page 31: ...0xn04 D0 RO RxACK D1 RO TxACK D2 4 HDLC Tx Last Character Length encoded as follows 000 8 bits 001 1 bit 010 2 bits 011 3 bits 100 4 bits 101 5 bits 110 6 bits 111 7 bits D5 Reserved D6 RO Loop Sendi...

Page 32: ...follows 00 All Zeros 01 All Ones 10 Alternating 1 0 11 Alternating 0 1 D2 3 Tx Preamble Length encoded as follows 00 8 bits 01 16 bits 10 32 bits 11 64 bits D4 Tx Flag Preamble D6 7 Tx Status Block Tr...

Page 33: ...0011 CRC Byte 1 00100 Rx FIFO Write 00101 Clock Multiplexer Outputs 00110 CTR0 and CTR1 Counters 00111 Clock Multiplexer Inputs 01000 DPLL State 01001 Low Byte of Shifters 01010 CRC Byte 2 01011 CRC B...

Page 34: ...Transmit Clock Source encoded as follows 000 Disabled 001 RxC Pin 010 TxC Pin 011 DPLL Output 100 BRG0 Output 101 BRG1 Output 110 CTR0 Output 111 CTR1 Output D6 7 RW DPLL Clock Source encoded as foll...

Page 35: ...t 1 D5 RW BRG1 Enable D4 RW BRG1 Single Cycle Continuous D6 7 Tx ACK Pin Control encoded as follows 00 3 State Output 01 Tx Acknowledge Input 10 Output 0 11 Output 1 2 3 10 2 High LOC 0xn13 D0 D1 DPLL...

Page 36: ...ows 000 Input Pin 001 Rx Clock Output 010 Rx Byte Clock Output 011 SYNC Output 100 BRG0 Output 101 BRG1 Output 110 CTR0 Output 111 DPLL Rx Output D3 D5 TxC Pin Control encoded as follows 000 Input Pin...

Page 37: ...R 2 3 13 1 Low LOC 0xn18 D0 RW Device Status IE D1 RW I O Status IE D2 RW Transmit Data IE D3 RW Transmit Status IE D4 RW Receive Data IE D5 RW Receive Status IE D6 7 IE Command encoded as follows 00...

Page 38: ...W Device Status IUS D1 RW I O Status IUS D2 RW Transmit Data IUS D3 RW Transmit Status IUS D4 RW Receive Data IUS D5 RW Receive Status IUS D6 7 IUS Command encoded as follows 00 Null Command 01 Null C...

Page 39: ...ising Edge Only 10 Falling Edge Only 11 Both Edges 2 3 16 2 High LOC 0xn1F D0 1 RW TxREQ Interrupts encoded as follows 00 Disabled 01 Rising Edge Only 10 Falling Edge Only 11 Both Edges D3 2 RW RxREQ...

Page 40: ...Bits 011 3 Bits 100 4 Bits 101 5 Bits 110 6 Bits 111 7 Bits D5 RW Rx Parity Enable D6 7 Rx Parity Sense encoded as follows 00 Even 01 Odd 10 Space 11 Mark 2 3 18 2 High LOC 0xn23 D0 RW Queue Abort D1...

Page 41: ...Reserved 0101 Select FIFO Status 0110 Select FIFO Interrupt Level 0111 Select FIFO Request Level 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111...

Page 42: ...2 3 23 RECEIVE CHARACTER COUNT REGISTER RCCR 2 3 23 1 Low LOC 0xn2C D0 7 RO RCC 7 0 2 3 23 2 High LOC 0xn2D D0 7 RO RCC 15 8 2 3 24 TIME CONSTANT 0 REGISTER TC0R 2 3 24 1 Low LOC 0xn2E D0 7 RW TC0 7...

Page 43: ...Value D3 4 Polynomial Tx CRC encoded as follows 00 CRC CCITT 01 CRC 16 10 CRC 32 11 Reserved D5 7 Tx Data Encoding encoded as follows 000 NRZ 001 NRZB 010 NRZI Mark 011 NRZI Space 100 Biphase Mark 10...

Page 44: ...bort 1010 Reserved 1011 Reserved 1100 Reset DLE Inhibit 1101 Set DLE Inhibit 1110 Reset EOF EOM 1111 Set EOF EOM 2 3 27 TRANSMIT INTERRUPT CONTROL REGISTER TICR 2 3 27 1 Low LOC 0xn36 D0 RW TC1R Read...

Page 45: ...MIT REGISTER TCLR 2 3 29 1 Low LOC 0xn3A D0 7 RW TCL 7 0 2 3 29 2 High LOC 0xn3B D0 7 RW TCL 15 8 2 3 30 TRANSMIT CHARACTER COUNT REGISTER TCCR 2 3 30 1 Low LOC 0xn3C D0 7 RO TCC 7 0 2 3 30 2 High LOC...

Page 46: ...ace Unless the user is writing a device driver the details of the PCI interface Chapter 2 may be skipped 3 1 PCI CONFIGURATION REGISTERS The PCI device configuration for the PCI PMC HPDI32 is fully PC...

Page 47: ...enabled D7 Wait Cycle Control Controls whether the device does address data stepping A 0 indicates the device never does address data stepping Note Hardcoded to 0 D8 SERR Enable A 1 allows the device...

Page 48: ...is bit to be set 1 PCI9080 detected a parity error during a PCI address phase 2 PCI9080 detected a data parity error when it was the target of a write 3 PCI9080 detected a data parity error when perfo...

Page 49: ...Memory Space Indicator A 1 indicates the register maps into I O space Note Hardcoded to 1 D1 Reserved D7 2 I O Base Address Default Size 256 bytes Note Hardcoded to 0 D31 8 I O Base Address Base Addre...

Page 50: ...1 14 PCI INTERRUPT PIN REGISTER OFFSET 0X3D RESET 0X01 D7 0 Interrupt Pin register Indicates which interrupt pin the device uses 01 INTA Note PCI 9080 supports only one PCI interrupt pin INTA 3 1 15 P...

Page 51: ...Local Accesses 0x00000000 0x1C 0x9C Y Range for Direct Master to PCI Unused 0x00000000 0x20 0xA0 Y Local Base Address for Direct Master to PCI Memory Unused 0x00000000 0x24 0xA4 Y Local Base Address f...

Page 52: ...vice Vendor ID or SubDevice SubVendor ID D31 30 Reserved 3 2 3 BIG LITTLE ENDIAN DESCRIPTOR REGISTER PCI 0X0C Since local bus is little endian all bits should be left zero 3 2 4 LOCAL ADDRESS SPACE 0...

Page 53: ...lbox Register 7 Unused 0x00000000 0x60 0xE0 Y PCI to Local Doorbell Register Unused 0x00000000 0x64 0xE4 Y Local to PCI Doorbell Register Unused 0x00000000 0x68 0xE8 Y Interrupt Control Status 0x00000...

Page 54: ...2 SERIAL EEPROMCONTROL PCI COMMAND CODES USER I O CONTROL INIT CONTROL REGISTER PCI 0X6C RESET 0X0X001767E D3 0 PCI Read Command Code for DMA D7 4 PCI Write Command Code for DMA D11 8 PCI Memory Read...

Page 55: ...Unused 0x00000000 0xA4 0x124 Y DMA Channel 1 Descriptor Pointer Register Unused 0x00000000 0xA8 0x128 Y DMA Channel 1Command Status Register DMA Channel 0 Command Status Register 0x00000010 0xAC 0x12C...

Page 56: ...must start and end at the Cache Line Boundaries D14 DMA EOT End of Transfer Enable Unused D15 DMA Stop Data Transfer Mode A 0 sends a BLAST to terminate DMA transfer Note This bit should always be set...

Page 57: ...2 3 4 8 DMA THRESHOLD REGISTER PCI 0XB0 D3 0 DMA Channel 0 PCI to Local Almost Full C0PLAF D7 4 DMA Channel 0 Local to PCI Almost Empty C0LPAE D11 8 DMA Channel 0 Local to PCI Almost Full C0LPAF D15...

Page 58: ...by the user Each serial communication channel provides two 32 bit registers for setting these values a TX FIFO Almost Register and an RX FIFO Almost Register Each of these registers if further broken...

Page 59: ...which may be utilized by the application code or device driver to perform various operations Interrupt sources may include but are not limited to receive FIFO buffer almost empty sync word detection...

Page 60: ...There is a 68 pin DSUB user I O interface connector PLUG mounted soldered to the front edge of the board Ref Des PA2 for row A PB2 for row B The part number is P50E 068PI SRI TG manufacturer Robinsen...

Page 61: ...17 Channel 4 Lwr Cable TX RX Clk 51 Channel 2 Lwr Cable TX RX Clk 18 Channel 4 Lwr Cable TX RX Clk 52 Channel 2 Upr Cable TXD RXD 19 Channel 4 Upr Cable TXD RXD 53 Channel 2 Upr Cable TXD RXD 20 Chann...

Page 62: ...then the jumpers should be installed If the Zilog is going to generate an output clock to the cable then some of the jumpers should not be installed The Zilog Clock Select Jumpers are 2x8 the pin out...

Page 63: ...PCI SIO4 User Manual General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 56...

Page 64: ...PCI SIO4 User Manual General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 57...

Page 65: ...educe the risk of software overhead Standard configuration of the SIO4 contains 32k byte deep FIFOs 6 0 2 INTERFACE CABLE General Standards Corporation can provide an interface cable for the SIO4 boar...

Page 66: ...PCI SIO4 User Manual General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 59...

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