PCI-SIO4 User Manual
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
43
D15:0
Subsystem Vendor ID – 0x10B5 = PLX Technology
D31:16
Subsystem Device ID – 0x2400 = General Standards Corporation HPDI32).
3.1.13 PCI
I
NTERRUPT
L
INE
R
EGISTER
:
(O
FFSET
0
X
3C,
R
ESET
0
X
00)
D7:0
Interrupt Line Routing Value
Indicates which input of the system interrupt controller(s) to which the interrupt line of
the device is connected.
3.1.14 PCI
I
NTERRUPT
P
IN
R
EGISTER
:
(O
FFSET
0
X
3D,
R
ESET
0
X
01)
D7:0
Interrupt Pin register. Indicates which interrupt pin the device uses.
01=INTA#
Note:
PCI 9080 supports only one PCI interrupt pin (INTA#).
3.1.15 PCI
M
IN
_G
NT
R
EGISTER
:
(O
FFSET
0
X
3E,
R
ESET
0
X
00)
D7:0
Minimum Grant
Specifies the minimum burst period the device needs assuming a clock rate of 33 MHz.
Value is in 250 nsec increments. A ‘0’ indicates no stringent requirement.
3.1.16 PCI
M
AX
_L
AT
R
EGISTER
:
(O
FFSET
0
X
3F,
R
ESET
0
X
00)
D7:0
Maximum Latency
Specifies the maximum burst period the device needs assuming a clock rate of 33 MHz.
Value is in 250 nsec increments. A ‘0’ indicates no stringent requirement.
