PCI-SIO4 User Manual
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
51
CHAPTER 4: PROGRAMMING
4.0
INTRODUCTION
This section was written for the user who is attempting to write his/her own device driver or would just like a
better understanding of how the SIO4 family of cards operates. Some of the operations listed in this section
may be performed by or differently from the same operation when using a General Standards provided
device driver. Please see the device driver documentation for specific differences.
4.1
RESETS
Each serial communication channel of the SIO4 provides three reset sources: a transmit FIFO buffer
reset, a receive FIFO buffer reset and a Zilog Z16C30 reset. Please note that performing a FIFO buffer
reset while data is present in that FIFO will cause the data to be lost. Also note: since each Zilog Z16C30
chip contains two serial channels, performing a Zilog reset to either channel will reset the entire chip.
For instance, performing a Zilog reset on either channel 1 or channel 2 will reset the entire Zilog chip,
clearing all registers for both channel 1 and channel 2. Likewise, performing a Zilog reset of either channel
3 or channel 4 will reset the second Zilog chip and clear all the registers for channel 3 and channel 4.
4.2
FIFO ALMOST FLAGS
The FIFO buffer chips utilized on the SIO4 provide a means by which the user can determine the
approximate amount of data in the FIFO. This mechanism is called FIFO almost full and FIFO almost
empty flags, and these are programmable by the user. Each serial communication channel provides two 32
bit registers for setting these values: a TX FIFO Almost Register, and an RX FIFO Almost Register. Each
of these registers if further broken up into two 16 bit portions, where the value in the upper 16 bits (D16 -
D31) is used to program the almost full FIFO flag, and the value in the lower 16 bits (D0 - D15) is used to
program the FIFO almost empty flag. The almost flags current status may be read from the respective
channel’s Control/Status register. These FIFO status bits are updated every 33 nanoseconds
.
Each value in the corresponding portion of the almost register represents the number of bytes from each
respective “end” of the FIFO. Meaning, a value of 0x00100010 in the FIFO almost register means that the
FIFO almost flags will be programmed to trigger at a point 0x10 bytes from each “end” of the FIFO. This
means that the almost empty flag will be asserted when the FIFO has (0x10 + 1) bytes in it, whereas the
almost full flag will be asserted when the FIFO has (Total FIFO size in bytes – 0x10) bytes in it. For the
standard 32Kbyte FIFO, an almost full value of 0x10 will cause the almost full flag to be asserted when the
FIFO has 32752 bytes of data (32768 – 16 or 0x8000 – 0x10).
The values placed in the FIFO almost registers are programmed to the FIFO chips whenever a FIFO reset is
performed; the proper steps to program these values are:
•
Program the respective FIFO almost register(s)
•
Perform a FIFO reset of the respective FIFO
•
The value in the almost register is now programmed into the FIFO chips
Please note: if the FIFO almost registers are left at a value of 0x0 during a FIFO reset, the almost flags will
be set to the FIFO chip manufacturer default of 7 bytes from empty and 7 bytes from full.
