PCI-SIO4 User Manual
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
15
accessing the local side of the board again. This bit is a self-timed pulse;
therefore, it is not necessary for software to return to clear this bit, it will clear
itself.
D2
Enable the Channel 2 Transmitters for the Upper portion of the cable (will drive the
cable)
Writing a ‘1’ to this bit will turn on the transmitters for the Channel 2 upper
portion of the cable. The signals that are turned on are the Channel 2 TxD and
Channel 2 CTS on the upper portion of the cable. This will cause these signals
on the cable to go from a tri-state condition to a driven state.
D3
Enable the Channel 2 Transmitters for the Lower portion of the cable (will drive the
Cable)
Writing a ‘1’ to this bit will turn on the transmitters for the Channel 2 lower
portion of the cable. The signals that are turned on are the Channel 2 TxD and
Channel 2 CTS on the lower portion of the cable. This will cause these signals
on the cable to go from a tri-state condition to a driven state.
D4
Enable the Channel 2 Receivers for the Upper portion of the cable (will load the cable)
Writing a ‘1’ to this bit will turn on the receivers for the Channel 2 upper portion
of the cable. The signals that are turned on are the Channel 2 RxD and Channel
2 DCD on the upper portion of the cable. This will cause these signals on the
cable to go from a tri-state condition to a loaded condition.
D5
Enable the Channel 2 Receivers for the Lower portion of the cable (will load the cable)
Writing a ‘1’ to this bit will turn on the receivers for the Channel 2 lower portion
of the cable. The signals that are turned on are the Channel 2 RxD and Channel
2 DCD on the lower portion of the cable. This will cause these signals on the
cable to go from a tri-state condition to a loaded condition.
D6
Reserved
D7
Reset Zilog for Channel 1-2 (Pulsed)
Writing a ‘1’ to this bit will cause the channel 1-2 Zilog Z16C30 USC to be
reset. This bit is a self-timed pulse; therefore, it is not necessary for software to
return to clear this bit, it will clear itself. Note, that after power up and after any
reset to this component, the next access to channel 1 or channel 2 USC must be a
write of 0x00 to offset 0x00 of channel 1 USC.
D8
Channel 2 Tx FIFO Empty
(TRUE == 0)
D9
Channel 2 Tx FIFO Almost Empty
(TRUE == 0)
D10
Channel 2 Tx FIFO Almost Full
(TRUE == 0)
D11
Channel 2 Tx FIFO Full
(TRUE == 0)
D12
Channel 2 Rx FIFO Empty
(TRUE == 0)
D13
Channel 2 Rx FIFO Almost Empty
(TRUE == 0)
D14
Channel 2 Rx FIFO Almost Full
(TRUE == 0)
D15
Channel 2 Rx FIFO Full
(TRUE == 0)
The FIFO status flags are active low indicators of the current FIFO status. These flags are
continuously being updated every 33ns. A value of ‘0’ indicates that the current status is true and
a value of ‘1’ indicates that it is not true. There are only 5 valid combinations for each nibble
(D8..D11 or D12..D15). These combinations are as follows:
0xC
1100
Almost Empty and Empty
0xD
1101
Almost Empty but not Empty
0xF
1111
In between Almost Empty and Almost Full
0xB
1011
Almost Full but not full
0x3
0011
Almost Full and Full
