PCI-SIO4 User Manual
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
21
D15
Status on Channel 4 Interrupt for USC Request Interrupt
Note:
A ‘1’, in any of these positions, will indicate that the corresponding source has either
performed a PCI interrupt or that the source for the interrupt is currently active; thus, could
perform a PCI interrupt if enabled in the interrupt control register. Whether or not the interrupt
was performed depends on the interrupt control register.
If the corresponding bit in the interrupt control register is a ‘0’, then the source has not
performed a PCI interrupt and is only indicating the current status of that source.
If the corresponding bit in the interrupt control register is a ‘1’, then the source has performed a
PCI interrupt and has latched itself. Writing a ‘1’ to the respective bit in the interrupt status
register clears the interrupt status bit. A second interrupt will not occur until after that status
bit has been cleared. The interrupts are not queued; hence, each potential interrupt should be
observed when identifying the source and clearing the status register. Failure to do so could
prevent any other interrupts from occurring.
2.2
USC REGISTERS
2.2.1
C
HANNEL
1
USC:
(LOC
0
X
100
TO
0
X
17E)
D0..7
Channel 1 USC Data (Zilog Data Bus, See Serial Controller Registers)
2.2.2
C
HANNEL
2
USC:
(LOC
0
X
200
TO
0
X
27E)
D0..7
Channel 2 USC Data (Zilog Data Bus, See Serial Controller Registers)
2.2.3
C
HANNEL
3
USC:
(LOC
0
X
300
0
X
37E)
D0..7
Channel 3 USC Data (Zilog Data Bus, See Serial Controller Registers)
2.2.4
C
HANNEL
4
USC:
(LOC
0
X
400
TO
0
X
47E)
D0..7
Channel 4 USC Data (Zilog Data Bus, See Serial Controller Registers)
