Universal Serial Bus Interface – On-The-Go Module
MCF52277 Reference Manual, Rev. 1
20-26
Freescale Semiconductor
20.3.4.6
Device Address Register (DEVICEADDR)
This register is not defined in the EHCI specification. For device mode, the upper seven bits of this register
represent the device address. After any controller or USB reset, the device address is set to the default
address (0). The default address matches all incoming addresses. Software reprograms the address after
receiving a SET_ADDRESS descriptor.
The host and device mode functions share this register. In device mode, it is the DEVICEADDR register;
in host mode, it is the PERIODICLISTBASE register. See
Section 20.3.4.5, “Periodic Frame List Base
Address Register (PERIODICLISTBASE),”
for more information.
20.3.4.7
Current Asynchronous List Address Register (ASYNCLISTADDR)
The ASYNCLISTADDR register contains the address of the next asynchronous queue head to executed
by the host.
The host and device mode functions share this register. In host mode, it is the ASYNCLISTADDR register;
in device mode, it is the EPLISTADDR register. See
Section 20.3.4.8, “Endpoint List Address Register
for more information.
Table 20-24. PERIODICLISTBASE Field Descriptions
Field
Description
31–12
PERBASE
Base Address.
These bits correspond to memory address signal [31:12]. Used only in the host mode
11–0
Reserved, must be cleared.
Address: 0xFC0B_0154 (DEVICEADDR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
USBADR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-21. Device Address Register (DEVICEADDR)
Table 20-25. DEVICEADDR Field Descriptions
Field
Description
31–25
USBADR
Device Address. This field corresponds to the USB device address.
24–0
Reserved, must be cleared.
Address: 0xFC0B_0158 (ASYNCLISTADDR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
ASYBASE
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-22. Current Asynchronous List Address Register (ASYNCLISTADDR)
Summary of Contents for MCF52277
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Page 60: ...Signal Descriptions MCF52277 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 128: ...Static RAM SRAM MCF52277 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 140: ...Clock Module MCF52277 Reference Manual Rev 1 7 12 Freescale Semiconductor...
Page 172: ...Chip Configuration Module CCM MCF52277 Reference Manual Rev 1 9 16 Freescale Semiconductor...
Page 180: ...Serial Boot Facility SBF MCF52277 Reference Manual Rev 1 10 8 Freescale Semiconductor...
Page 188: ...Reset Controller Module MCF52277 Reference Manual Rev 1 11 8 Freescale Semiconductor...
Page 210: ...Crossbar Switch XBS MCF52277 Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 542: ...FlexCAN MCF52277 Reference Manual Rev 1 23 32 Freescale Semiconductor...
Page 724: ...UART Modules MCF52277 Reference Manual Rev 1 30 34 Freescale Semiconductor...
Page 740: ...I2 C Interface MCF52277 Reference Manual Rev 1 31 16 Freescale Semiconductor...
Page 790: ...Debug Module MCF52277 Reference Manual Rev 1 32 50 Freescale Semiconductor...
