Freescale Semiconductor MCF52277, Reference Manual

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Cache
MCF52277 Reference Manual, Rev. 1
5-8 Freescale Semiconductor
If the referenced address is mapped into the SRAM module, that module services the request in a single
cycle. In this case, data accessed from the cache is simply discarded and no external memory references
are generated. If the address is not mapped into the SRAM space, the cache handles the request in the
normal fashion.
5.3.2 Memory Reference Attributes
For every memory reference the ColdFire core or the debug module generates, a set of effective attributes
is determined based on the address and the access control registers (ACRs). This set of attributes includes
the cacheable/non-cacheable definition, the precise/imprecise handling of operand write, and the
write-protect capability.
In particular, each address is compared to the values programmed in the ACRs. If the address matches one
of the ACR values, the access attributes from that ACR are applied to the reference. If the address does
not match either ACR, then the default value defined in the cache control register (CACR) is used. The
specific algorithm is as follows:
if (address == ACR0_address including mask)
Effective Attributes = ACR0 attributes
else if (address == ACR1_address including mask)
Effective Attributes = ACR1 attributes
else Effective Attributes = CACR default attributes
5.3.3 Cache Coherency and Invalidation
The cache does not monitor data references for accesses to cached instructions. Therefore, software must
maintain instruction cache coherency by invalidating the appropriate cache entries after modifying code
segments if instructions are cached.
The cache invalidation can be performed in several ways. For the instruction- or data-only configurations,
setting CACR[CINV] forces the entire cache to be marked as invalid. The invalidation operation requires
512 cycles because the cache sequences through the entire tag array, clearing a single location each cycle.
For the split configuration, CACR[INVI] and CACR[INVD] can be used in addition to CACR[CINV] to
clear the entire cache, only the instruction half, or only the data half. Any subsequent fetch accesses are
postponed until the invalidation sequence is complete.
The privileged CPUSHL instruction can invalidate a single cache line. When this instruction is executed,
the cache entry defined by bits [12:4] of the source address register is invalidated, provided CACR[CPDI]
is cleared. For the split data/instruction cache configuration, software directly controls bit 12 that selects
whether an instruction cache or data cache line is being accessed.
These invalidation operations can be initiated from the ColdFire core or the debug module.
5.3.4 Reset
A hardware reset clears the CACR and disables the cache. The contents of the tag array are not affected
by the reset. Accordingly, the system startup code must explicitly perform a cache invalidation by setting
CACR[CINV] before the cache can be enabled.