Enhanced Direct Memory Access (eDMA)
MCF52277 Reference Manual, Rev. 1
Freescale Semiconductor
17-5
NOTE
For proper operation, writes to the EDMA_CR register must only be
performed when the DMA channels are inactive (TCR
n
_CSR[ACTIVE]
bits are cleared).
17.6.2
eDMA Error Status Register (EDMA_ES)
The EDMA_ES provides information concerning the last recorded channel error. Channel errors can be
caused by a configuration error (an illegal setting in the transfer-control descriptor or an illegal priority
register setting in fixed-arbitration mode) or an error termination to a bus master read or write cycle.
A configuration error is reported when the starting source or destination address, source or destination
offsets, minor loop byte count, or the transfer size represent an inconsistent state. Each of these possible
causes are detailed in the below list:
•
The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries
•
The minor loop byte count must be a multiple of the source and destination transfer sizes.
•
All source reads and destination writes must be configured to the natural boundary of the
programmed transfer size respectively.
Address: 0xFC04_4000 (EDMA_CR)
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
ERCA EDBG
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 17-3. eDMA Control Register (EDMA_CR)
Table 17-3. eDMA_CR Field Descriptions
Field
Description
31–3
Reserved, must be cleared.
2
ERCA
Enable round robin channel arbitration.
0 Fixed priority arbitration is used for channel selection.
1 Round robin arbitration is used for channel selection.
1
EDBG
Enable debug.
0 When in debug mode the DMA continues to operate.
1 When in debug mode, the eDMA stalls the start of a new channel. Executing channels are allowed to complete.
Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
0
Reserved, must be cleared.
Summary of Contents for MCF52277
Page 22: ...MCF52277 Reference Manual Rev 1 Freescale Semiconductor xxii...
Page 32: ...MCF52277 Reference Manual Rev 0 xxxii Freescale Semiconductor...
Page 60: ...Signal Descriptions MCF52277 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 128: ...Static RAM SRAM MCF52277 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 140: ...Clock Module MCF52277 Reference Manual Rev 1 7 12 Freescale Semiconductor...
Page 172: ...Chip Configuration Module CCM MCF52277 Reference Manual Rev 1 9 16 Freescale Semiconductor...
Page 180: ...Serial Boot Facility SBF MCF52277 Reference Manual Rev 1 10 8 Freescale Semiconductor...
Page 188: ...Reset Controller Module MCF52277 Reference Manual Rev 1 11 8 Freescale Semiconductor...
Page 210: ...Crossbar Switch XBS MCF52277 Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 542: ...FlexCAN MCF52277 Reference Manual Rev 1 23 32 Freescale Semiconductor...
Page 724: ...UART Modules MCF52277 Reference Manual Rev 1 30 34 Freescale Semiconductor...
Page 740: ...I2 C Interface MCF52277 Reference Manual Rev 1 31 16 Freescale Semiconductor...
Page 790: ...Debug Module MCF52277 Reference Manual Rev 1 32 50 Freescale Semiconductor...
