DMA Serial Peripheral Interface (DSPI)
MCF52277 Reference Manual, Rev. 1
29-8
Freescale Semiconductor
29.3.2
DSPI Transfer Count Register (DSPI_TCR)
The DSPI_TCR contains a counter that indicates the number of SPI transfers made. The transfer counter
is intended to assist in queue management. Do not write to the DSPI_TCR while the DSPI is running.
29.3.3
DSPI Clock and Transfer Attributes Registers 0–7 (DSPI_CTAR
n
)
DSPI modules each contain eight clock and transfer attribute registers (DSPI_CTAR
n
) used to define
different transfer attribute configurations. Each DSPI_CTAR controls:
•
Frame size
•
Baud rate and transfer delay values
•
Clock phase
•
Clock polarity
•
MSB/LSB first
DSPI_CTARs support compatibility with the QSPI module in the ColdFire family of MCUs. At the
initiation of an SPI transfer, control logic selects the DSPI_CTAR that contains the transfer’s attributes.
Do not write to the DSPI_CTARs while the DSPI is running.
In master mode, the DSPI_CTAR
n
registers define combinations of transfer attributes such as frame size,
clock phase and polarity, data bit ordering, baud rate, and various delays. When DSPI is configured as an
SPI master, the DSPI_PUSHR[CTAS] field in the command portion of the TX FIFO entry selects which
of the DSPI_CTAR registers is used on a per-frame basis.
In slave mode, a subset of the bit fields in the DSPI_CTAR0 registers sets the slave transfer attributes. See
the individual bit descriptions for details on which bits are used in slave modes.
Address: 0xFC05_C008 (DSPI_TCR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
SPI_TCNT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 29-3. DSPI_TCR Register
Table 29-4. DSPI_TCR Field Descriptions
Field
Description
31–16
SPI_TCNT
SPI transfer counter. Counts the number of SPI transfers the DSPI makes. The SPI_TCNT field increments every
time the last bit of an SPI frame transmits. A value written to SPI_TCNT presets the counter to that value.
SPI_TCNT is reset to 0 at the beginning of the frame when the CTCNT field is set in the executing SPI command.
The transfer counter wraps around. Incrementing the counter past 65535 resets the counter to 0.
15–0
Reserved, must be cleared
Summary of Contents for MCF52277
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Page 60: ...Signal Descriptions MCF52277 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 128: ...Static RAM SRAM MCF52277 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 140: ...Clock Module MCF52277 Reference Manual Rev 1 7 12 Freescale Semiconductor...
Page 172: ...Chip Configuration Module CCM MCF52277 Reference Manual Rev 1 9 16 Freescale Semiconductor...
Page 180: ...Serial Boot Facility SBF MCF52277 Reference Manual Rev 1 10 8 Freescale Semiconductor...
Page 188: ...Reset Controller Module MCF52277 Reference Manual Rev 1 11 8 Freescale Semiconductor...
Page 210: ...Crossbar Switch XBS MCF52277 Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 542: ...FlexCAN MCF52277 Reference Manual Rev 1 23 32 Freescale Semiconductor...
Page 724: ...UART Modules MCF52277 Reference Manual Rev 1 30 34 Freescale Semiconductor...
Page 740: ...I2 C Interface MCF52277 Reference Manual Rev 1 31 16 Freescale Semiconductor...
Page 790: ...Debug Module MCF52277 Reference Manual Rev 1 32 50 Freescale Semiconductor...
