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MCF52277 Reference Manual, Rev. 1

5-6

Freescale Semiconductor

 

5.2.2

Access Control Registers (ACR0, ACR1)

The ACRs provide a definition of memory reference attributes for two memory regions (one per ACR). 
This set of effective attributes is defined for every memory reference using the ACRs or the set of default 
attributes contained in the CACR. The ACRs are examined for every processor memory reference not 
mapped to the SRAM memories.

The ACRs are 32-bit, write-only supervisor control register. They are accessed in the CPU address space 
via the MOVEC instruction with an Rc encoding of 0x004 and 0x005. The ACRs can be read when in 
background debug mode (BDM). Therefore, the register diagram, 

Figure 5-3

, is shown as read/write. At 

system reset, both registers are disabled with ACR

n

[EN] cleared.

NOTE

Peripheral space (0xE000_0000-0xFFFF_FFFF) should not be cached. The 
combination of the CACR defaults and the two ACR

n

 registers must define 

the non-cacheable attribute for this address space.

Table 5-4. Cache Invalidate All as Defined by CACR

CACR

[DISI]

CACR

[DISD]

CACR

[INVI]

CACR

[INVD]

Configuration

Operation

0

0

0

0

Split  Instruction/
Data Cache

Invalidate all entries in 4-KByte instruction 
cache and 4-KByte data cache

0

0

0

1

Split  Instruction/
Data Cache

Invalidate only 4 KByte data cache

0

0

1

0

Split  Instruction
Data Cache

Invalidate only 4 KByte instruction cache

0

0

1

1

Split  Instruction/
Data Cache

No invalidate

1

0

x

x

Instruction Cache

Invalidate 8 KByte instruction cache

0

1

x

x

Data Cache

Invalidate 8 KByte data cache

BDM: 0x004 (ACR0)

0x005 (ACR1)

Access: Supervisor write-only

BDM read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

AB

AM

EN

SM

0

0

0

0

0

0

CM BWE

0

0

WP

0

0

W

Reset – – – – – – – – – – – – – – – –

0

–

–

0

0

0

0

0

0

–

–

0

0

–

0

0

Figure 5-3.  Access Control Registers (ACR

n

)

Summary of Contents for MCF52277

Page 1: ...MCF52277 Reference Manual Devices Supported MCF52274 MCF52277 Document Number MCF52277RM Rev 1 04 2008...

Page 2: ...particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including wit...

Page 3: ...t Controller 1 5 1 3 7 System Control Module 1 5 1 3 8 Crossbar Switch Module 1 5 1 3 9 Liquid Crystal Display Controller LCDC 1 6 1 3 10 ADC and Touch Screen Controller 1 6 1 3 11 Universal Serial Bu...

Page 4: ...Width Modulation PWM Module Signals 2 10 2 3 12 Universal Serial Bus USB On the Go Signals 2 11 2 3 13 Touschreen Controller ADC Signals 2 11 2 3 14 I2C I O Signals 2 11 2 3 15 DMA Serial Peripheral I...

Page 5: ...2 Mask Register MASK 4 5 4 2 3 Accumulator Registers ACC0 3 4 6 4 2 4 Accumulator Extension Registers ACCext01 ACCext23 4 7 4 3 Functional Description 4 8 4 3 1 Fractional Operation Mode 4 10 4 3 2 EM...

Page 6: ...Description 7 8 7 3 1 PLL Frequency Multiplication Factor Select 7 8 7 3 2 Lock Conditions 7 9 7 3 3 Loss of Lock 7 9 7 3 4 System Clock Modes 7 10 7 3 5 Clock Operation During Reset 7 11 Chapter 8 P...

Page 7: ...Configuration 9 14 9 4 3 Output Pad Strength Configuration 9 14 9 4 4 Chip Select Configuration 9 14 9 4 5 Low Power Configuration 9 15 Chapter 10 Serial Boot Facility SBF 10 1 Introduction 10 1 10 1...

Page 8: ...rol Register CWCR 12 7 12 2 4 Core Watchdog Service Register CWSR 12 8 12 2 5 SCM Interrupt Status Register SCMISR 12 8 12 2 6 Burst Configuration Register BCR 12 9 12 2 7 Core Fault Address Register...

Page 9: ...igital I O Timing 14 27 14 5 Initialization Application Information 14 28 Chapter 15 Interrupt Controller Modules 15 1 Introduction 15 1 15 1 1 68K ColdFire Interrupt Architecture Overview 15 1 15 2 M...

Page 10: ...5 1 External Signal Timing 17 3 17 6 Memory Map Register Definition 17 4 17 6 1 eDMA Control Register EDMA_CR 17 4 17 6 2 eDMA Error Status Register EDMA_ES 17 5 17 6 3 eDMA Enable Request Register E...

Page 11: ...Byte Enables Byte Write Enables FB_BE BWE 3 0 18 3 18 2 4 Output Enable FB_OE 18 3 18 2 5 Read Write FB_R W 18 3 18 2 6 Transfer Start FB_TS 18 3 18 2 7 Transfer Acknowledge FB_TA 18 3 18 3 Memory Ma...

Page 12: ...19 6 1 Page Management 19 27 19 6 2 Transfer Size 19 28 Chapter 20 Universal Serial Bus Interface On The Go Module 20 1 Introduction 20 1 20 1 1 Overview 20 1 20 1 2 Block Diagram 20 2 20 1 3 Feature...

Page 13: ...ister LCD_DCR 21 16 21 3 14 LCDC Refresh Mode Control Register LCD_RMCR 21 17 21 3 15 LCDC Interrupt Configuration Register LCD_ICR 21 18 21 3 16 LCDC Interrupt Enable Register LCD_IER 21 19 21 3 17 L...

Page 14: ...5 1 Touchscreen Mode 00 22 17 22 5 2 Touchscreen Mode 01 Single Round 22 19 22 5 3 Touchscreen Mode 01 Auto 22 20 22 5 4 Touchscreen Mode 10 Single Round 22 21 22 5 5 Touchscreen Mode 10 Auto 22 22 22...

Page 15: ...1 Overview 24 1 24 2 Memory Map Register Definition 24 2 24 2 1 PWM Enable Register PWME 24 3 24 2 2 PWM Polarity Register PWMPOL 24 4 24 2 3 PWM Clock Select Register PWMCLK 24 4 24 2 4 PWM Prescale...

Page 16: ...RCR 25 23 25 3 12 SSI Clock Control Register SSI_CCR 25 24 25 3 13 SSI FIFO Control Status Register SSI_FCSR 25 25 25 3 14 SSI AC97 Control Register SSI_ACR 25 27 25 3 15 SSI AC97 Command Address Regi...

Page 17: ...3 Sampling Timer 26 12 26 4 4 Minute Stopwatch 26 13 26 5 Initialization Application Information 26 13 26 5 1 Flow Chart of RTC Operation 26 13 26 5 2 Programming the Alarm or Time of Day Registers 2...

Page 18: ...ip Selects 2 4 DSPI_PCS 2 4 29 4 29 2 4 Serial Input DSPI_SIN 29 4 29 2 5 Serial Output DSPI_SOUT 29 4 29 2 6 Serial Clock DSPI_SCK 29 5 29 3 Memory Map Register Definition 29 5 29 3 1 DSPI Module Con...

Page 19: ...0 9 30 3 6 UART Receive Buffers URBn 30 11 30 3 7 UART Transmit Buffers UTBn 30 12 30 3 8 UART Input Port Change Registers UIPCRn 30 12 30 3 9 UART Auxiliary Control Register UACRn 30 13 30 3 10 UART...

Page 20: ...31 4 3 Post Transfer Software Response 31 13 31 4 4 Generation of STOP 31 13 31 4 5 Generation of Repeated START 31 14 31 4 6 Slave Mode 31 14 31 4 7 Arbitration Lost 31 14 Chapter 32 Debug Module 32...

Page 21: ...escription 33 2 33 2 1 JTAG Enable JTAG_EN 33 2 33 2 2 Test Clock Input TCLK 33 3 33 2 3 Test Mode Select Breakpoint TMS BKPT 33 3 33 2 4 Test Data Input Development Serial Input TDI DSI 33 3 33 2 5 T...

Page 22: ...MCF52277 Reference Manual Rev 1 Freescale Semiconductor xxii...

Page 23: ...ing any warranty of merchantability non infringement fitness for any particular purpose or any warranty otherwise arising out of any proposal specification or sample Intel disclaims all liability incl...

Page 24: ...e different types of reset that can occur Chapter 12 System Control Module SCM describes the functionality of the SCM which provides the programming model for peripheral access control the software co...

Page 25: ...IT timers including operation in low power mode Chapter 28 DMA Timers DTIM0 DTIM3 describes the configuration and operation of the DMA timer modules These 32 bit timers provide input capture and refer...

Page 26: ...hin a reference manual an errata document will be issued before the next published release of the reference manual These addenda errata are intended for use with the corresponding reference manuals Da...

Page 27: ...er Figure Conventions This document uses the following conventions for the register reset values Undefined at reset u Unaffected by reset signal_name Reset value is determined by the polarity of the i...

Page 28: ...t BSDL Boundary scan description language CODEC Code decode DAC Digital to analog conversion DMA Direct memory access DSP Digital signal processing EA Effective address FIFO First in first out GPIO Ge...

Page 29: ...itter USB Universal serial bus Table ii Notational Conventions Instruction Operand Syntax Opcode Wildcard cc Logical condition example NE for not equal Register Specifications An Any address register...

Page 30: ...t size Operand data size byte B word W longword L bc Instruction and data caches dc Data cache ic Instruction cache vector Identifies the 4 bit vector number for trap instructions identifies an indire...

Page 31: ...is false and the optional else clause is present the operations after else are performed If the condition is false and else is omitted the instruction performs no operation Refer to the Bcc instructi...

Page 32: ...MCF52277 Reference Manual Rev 0 xxxii Freescale Semiconductor...

Page 33: ...77 device However it also pertains to the MCF52274 See the following section for a summary of differences between the various devices of the MCF5227x family 1 1 MCF5227x Family Comparison The followin...

Page 34: ...onous Serial Interface SSI I2 C DSPI UARTs 3 3 32 bit DMA Timers 4 4 Periodic Interrupt Timers PIT 2 2 PWM Module Edge Port Module EPORT General Purpose I O Module GPIO JTAG IEEE 1149 1 Test Access Po...

Page 35: ...PORT Edge port module GPIO General Purpose Input Output Module I2 C Inter Intergrated Circuit INTC Interrupt controller JTAG Joint Test Action Group interface LCD Liquid crystal display PIT Programmab...

Page 36: ...controller Liquid crystal display controller with support up to 4096 4096 pixels ADC and touchscreen controller FlexCAN module 4 32 bit timers with DMA support DMA supported serial peripheral interfa...

Page 37: ...disable of external clock input for low power consumption 1 3 5 Chip Configuration Module CCM System configuration during reset Bus monitor Configurable output pad drive strength control Unique part i...

Page 38: ...urements Supports 4 5 7 and 8 wire touch screen configurations Up to 8 auxiliary input channels are available for general purpose ADC measurements the number of the auxiliary input channels are define...

Page 39: ...dent primary and secondary wait states per chip select Programmable address setup and hold time with respect to chip select assertion per transfer direction Glueless interface to SRAM devices with or...

Page 40: ...countdown timer with interrupt Programmable daily alarm with interrupt Sampling timer with interrupt Once per day once per hour once per minute and once per second interrupts Operation determined by r...

Page 41: ...Error detection capabilities 1 3 22 I2 C Module Interchip bus interface for EEPROMs LCD controllers A D converters and keypads Fully compatible with industry standard I2 C bus Master or slave modes s...

Page 42: ...ns Various unused peripheral pins may be used as GPIO 1 3 27 System Debug Support Background debug mode BDM Revision B Real time debug support with four PC breakpoint registers and a pair of address b...

Page 43: ...ernal Peripheral Space The internal peripheral space contains locations for all internal registers used to program and control the device s functional blocks and external interfaces Table 1 3 summariz...

Page 44: ...oldfire 0xFC07_8000 30 DMA Timer 2 0xFC07_C000 31 DMA Timer 3 0xFC08_0000 32 PIT 0 0xFC08_4000 33 PIT 1 0xFC09_0000 36 PWM 0xFC09_4000 37 Edge Port 0xFC0A_0000 40 CCM Reset Controller Power Management...

Page 45: ...ive low signals such as SD_SRAS and TA are indicated with an overbar 2 2 Signal Properties Summary The below table lists the signals grouped by functionality NOTE In this table and throughout this doc...

Page 46: ...4 O SDVDD 143 142 C11 D11 FB_A 21 16 O SDVDD 141 139 137 135 A12 B12 C12 B13 A13 A14 FB_A 15 14 SD_BA 1 0 O SDVDD 131 130 B14 C13 FB_A 13 11 SD_A 13 11 O SDVDD 129 127 C14 D12 D13 FB_A10 O SDVDD 126 D...

Page 47: ...Interrupts Port4 IRQ7 PIRQ7 I EVDD 162 D7 IRQ4 PIRQ4 DREQ0 DSPI_PCS4 5 I EVDD 161 C7 IRQ1 PIRQ1 USB_CLKIN SSI_CLKIN I EVDD 160 B7 LCD Controller6 LCD_D 17 16 6 PLCDDH 1 0 LCD_D 11 10 O EVDD 9 8 E3 E4...

Page 48: ...D 99 K14 ADC ADC_IN 7 0 I VDD_ ADC 82 85 87 90 P12 N12 P13 N13 P14 N14 M13 M14 ADC_REF I VDD_ ADC 86 M12 I2C I2C_SCL PI2C1 CANTX U2TXD U I O EVDD 168 C5 I2C_SDA PI2C0 CANRX U2RXD U I O EVDD 167 D5 DSP...

Page 49: ...ONTRAST I EVDD 165 B6 DT0IN PTIMER0 DT0OUT LCD_REV I EVDD 166 A6 BDM JTAG9 PST 3 0 O EVDD L9 M9 N9 P9 DDATA 3 0 O EVDD L10 M10 N10 P10 ALLPST O EVDD 76 JTAG_EN D I EVDD 79 K10 PSTCLK TCLK U O EVDD 74...

Page 50: ...controlled by RESET When asserted these pins are configured for serial boot when negated the pins are configured for DSPI 8 Pull up when the serial boot facility SBF controls the pin 9 If JTAG_EN is a...

Page 51: ...C Crystal RTC_XTAL Oscillator output to RTC crystal O FlexBus Clock Out FB_CLK Reflects the internal bus clock or one half the core system clock fsys 2 O USB Clock In USB_CLKIN This pin allows the use...

Page 52: ...processor recognizes FB_TA the bus cycle is terminated I Read Write FB_R W Indicates direction of the data transfer on the bus for SRAM accesses A logic 1 indicates a read from a slave device and a lo...

Page 53: ...e O Table 2 8 SBF Signals Signal Name Abbreviation Function I O Chip Select SBF_CS Chip select used to access external SPI memory O Clock SBF_CK 25 MHz clock source for external SPI memory O Data In S...

Page 54: ...direction Active matrix Output enable to enable data to be shifted onto the display O Contrast LCD_CONTRAST Controls the LCD bias voltage for contrast control O Power Save LCD_PS Controls signal outpu...

Page 55: ...has occurred on USB data bus I Table 2 15 Touchscreen ADC Signals Signal Name Abbreviation Function I O ADC Reference ADC_REF External ADC reference voltage I ADC Inputs ADC_IN 7 0 Touchscreen and or...

Page 56: ...2 18 UART Module Signals Signal Name Abbreviation Function I O Transmit Serial Data Output UnTXD Data is shifted out lsb first at the falling edge of the serial clock source Output is held high when t...

Page 57: ...med to cause events in the respective timer It can clock the event counter or provide a trigger to the timer value capture logic I DMA Timer n Output DTnOUT Output from respective timer O Table 2 21 D...

Page 58: ...essor clock status is unrelated to the current bus transfer The PSTCLK signal can be used by the development system to know when to sample PST 3 0 Only present on the BGA device MCF52277 O All Process...

Page 59: ...PLL Analog Supply VDD_A_PLL Dedicated power supply signal to isolate the sensitive PLL analog VCO circuitry from the normal levels of noise present on the digital power supply Oscillator VDD_OSC VSS_...

Page 60: ...Signal Descriptions MCF52277 Reference Manual Rev 1 2 16 Freescale Semiconductor...

Page 61: ...es the V2 ColdFire core is comprised of two separate pipelines decoupled by an instruction buffer Figure 3 1 V2 ColdFire Core Pipelines The instruction fetch pipeline IFP is a two stage pipeline for p...

Page 62: ...it is required by the OEP For register to register and register to memory store operations the instruction passes through both OEP stages once For memory to register and read modify write memory oper...

Page 63: ...ister CACR 32 bit access control registers ACR0 ACR1 Table 3 1 ColdFire Core Programming Model BDM1 Register Width bits Access Reset Value Written with MOVEC Section Page Supervisor User Access Regist...

Page 64: ...004 5 Access Control Register 0 1 ACR0 1 32 R W See Section Yes 3 2 7 3 7 0x800 User Supervisor A7 Stack Pointer OTHER_A7 32 R W Contents of location 0x0000_0000 No 3 2 3 3 5 0x801 Vector Base Registe...

Page 65: ...stem to determine based on the setting of SR S the mapping of A7 and OTHER_A7 to the two program visible definitions SSP and USP This functionality is enabled by setting the enable user stack pointer...

Page 66: ...re 3 4 Stack Pointer Registers A7 and OTHER_A7 BDM LSB of Status Register SR Access User read write BDM read write 7 6 5 4 3 2 1 0 R 0 0 0 X N Z V C W Reset 0 0 0 Figure 3 5 Condition Code Register CC...

Page 67: ...ine attributes for user defined memory regions These attributes include the definition of cache mode write protect and buffer write enables The ACRs are described in Section 5 2 2 Access Control Regis...

Page 68: ...SR Field Descriptions Field Description 15 T Trace enable When set the processor performs a trace exception after every instruction 14 Reserved must be cleared 13 S Supervisor user state 0 User mode 1...

Page 69: ...ress and two unidirectional 32 bit data buses This structure minimizes the core size without compromising performance to a large degree A more detailed view of the hardware structure within the two pi...

Page 70: ...ta is available As the prefetch data arrives in the IFP it can be loaded into the FIFO instruction buffer or gated directly into the OEP The V2 design uses a simple static conditional branch predictio...

Page 71: ...d and the components of the operand address base register from the RGF and displacement are selected DS Second the operand effective address is generated using the ALU execute engine AG Third the memo...

Page 72: ...taneously allowing single cycle execution See Figure 3 14 where the effective address is of the form ea x d16 Ax i e a 16 bit signed displacement added to a base register Ax Operand Execution Pipeline...

Page 73: ...4 V2 OEP Register to Memory The pipeline timing diagrams of Figure 3 15 depict the execution templates for these three classes of instructions In these diagrams the x axis represents time and the vari...

Page 74: ...ldFire based designs into a wide range of embedded systems they found certain frequently used instruction sequences that could be improved by the creation of additional instructions The original ISA d...

Page 75: ...e interrupt exception also forces the M bit to be cleared and the interrupt priority mask to set to current interrupt request level Table 3 4 Instruction Enhancements over Revision ISA_A Instruction D...

Page 76: ...vector contents determine the address of the first instruction of the desired handler After the instruction fetch for the first opcode of the handler has initiated exception processing terminates and...

Page 77: ...ns three unique fields A 4 bit format field at the top of the system stack is always written with a value of 4 5 6 or 7 by the processor indicating a two longword frame format See Table 3 6 There is a...

Page 78: ...s execution and initiates exception processing In this situation any address register updates attributable to the auto addressing modes for example An An have already been performed so the programmin...

Page 79: ...stack frame 3 3 4 3 Illegal Instruction Exception The ColdFire variable length instruction set architecture supports three instruction sizes 16 32 or 48 bits The first instruction word is known as the...

Page 80: ...or mode instructions There is one special case involving the HALT instruction Normally this opcode is a supervisor mode instruction but if the debug module s CSR UHE is set then this instruction can b...

Page 81: ...d when bits 15 12 of the opword are 0b1111 This exception is generated when attempting to execute an undefined line F opcode 3 3 4 9 Debug Interrupt See Chapter 32 Debug Module for a detailed explanat...

Page 82: ...red to force the processor to exit this halted state 3 3 4 15 Reset Exception Asserting the reset input signal RESET to the processor causes a reset exception The reset exception has the highest prior...

Page 83: ...er Defines the hardware microarchitecture version of ColdFire core 0001 V1 ColdFire core 0010 V2 ColdFire core This is the value used for this device 0011 V3 ColdFire core 0100 V4 ColdFire core 0101 V...

Page 84: ...B 0010 ISA_C 1000 ISA_A This is the value used for this device Else Reserved 3 0 DEBUG Debug module revision number Defines revision level of the debug module used in the ColdFire processor core 0000...

Page 85: ...igurable cache associativity 00 Four way 01 Direct mapped This is the value used for this device Else Reserved for future use 27 24 CCSZ Configurable cache size Indicates the amount of instruction dat...

Page 86: ...lving consecutive STORE operations is two cycles The MOVEM instruction uses a different set of resources and this stall does not apply 3 The OEP completes all memory accesses without any stall conditi...

Page 87: ...6 Ay 3 1 0 3 1 1 3 1 1 3 1 1 3 1 1 d8 Ay Xi SF 4 1 0 4 1 1 4 1 1 4 1 1 xxx w 3 1 0 3 1 1 3 1 1 3 1 1 xxx l 3 1 0 3 1 1 3 1 1 3 1 1 d16 PC 3 1 0 3 1 1 3 1 1 3 1 1 3 1 1 d8 PC Xi SF 4 1 0 4 1 1 4 1 1 4...

Page 88: ...1 0 0 FF1 Dx 1 0 0 NEG L Dx 1 0 0 NEGX L Dx 1 0 0 NOT L Dx 1 0 0 SCC Dx 1 0 0 SWAP Dx 1 0 0 TST B ea 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 TST W ea 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0...

Page 89: ...0 23 1 0 23 1 0 24 1 0 23 1 0 20 0 0 DIVS L ea Dx 35 0 0 38 1 0 38 1 0 38 1 0 38 1 0 DIVU L ea Dx 35 0 0 38 1 0 38 1 0 38 1 0 38 1 0 EOR L Dy ea 1 0 0 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 EORI L imm Dx...

Page 90: ...ea list 1 n n 0 1 n n 0 MOVEM L list ea 1 n 0 n 1 n 0 n NOP 3 0 0 PEA ea 2 0 1 2 0 1 4 3 0 1 5 2 0 1 PULSE 1 0 0 STLDSR imm 5 0 1 STOP imm 3 0 0 3 TRAP imm 15 1 2 TPF 1 0 0 TPF W 1 0 0 TPF L 1 0 0 UN...

Page 91: ...L ea y Rmask 4 0 0 4 0 0 MOVE L ea y Raccext01 1 0 0 1 0 0 MOVE L ea y Raccext23 1 0 0 1 0 0 MOVE L Raccx ea x 1 0 0 2 2 Storing an accumulator requires one additional processor clock cycle when satu...

Page 92: ...only a single cycle for execution but if preceded immediately by a load MAC or MSAC instruction the depth of the EMAC pipeline is exposed and the execution time is four cycles 3 3 5 7 Branch Instructi...

Page 93: ...and a single 32 bit accumulator The EMAC features a four stage pipeline optimized for 32 bit operands with a fully pipelined 32 32 multiply array and four 48 bit accumulators The first ColdFire MAC s...

Page 94: ...iplier array is optimized for single cycle pipelined operations with a possible accumulation after product generation This functionality is common in many signal processing applications The ColdFire c...

Page 95: ...7 0x809 MAC Accumulator 1 ACC1 32 R W Undefined 4 2 3 4 6 0x80A MAC Accumulator 2 ACC2 32 R W Undefined 4 2 3 4 6 0x80B MAC Accumulator 3 ACC3 32 R W Undefined 4 2 3 4 6 1 The values listed in this c...

Page 96: ...cumulator value 5 F I Fractional integer mode Determines whether input operands are treated as fractions or integers 0 Integers can be represented in signed or unsigned notation depending on the value...

Page 97: ...Ry RxSF ea y Rw 1 V Overflow Set if an arithmetic overflow occurs on a MAC or MSAC instruction indicating that the result cannot be represented in the limited width of the EMAC V is set only if a pro...

Page 98: ...rement the updated An value calculation is also shown Use of the post increment addressing mode An with the MASK is suggested for circular queue implementations Figure 4 3 Mask Register MASK 4 2 3 Acc...

Page 99: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Accumulator W Reset Table 4 5 ACC0 3 Field Descriptions Field Description 31 0 Accumulator Store 32 bits of the result of t...

Page 100: ...ntegers Signed fixed point fractional numbers The EMAC is optimized for single cycle pipelined 32 32 multiplications For word and longword sized integer input operands the low order 40 bits of the pro...

Page 101: ...ACCextn contents and 32 bit ACCn contents the specific definitions are if MACSR 6 5 00 signed integer mode Complete Accumulator 47 0 ACCextn 15 0 ACCn 31 0 if MACSR 6 5 01 or 11 signed fractional mod...

Page 102: ...VEM instruction can efficiently move large data blocks by generating line sized burst references The ability to load an operand simultaneously from memory into a register and execute a MAC instruction...

Page 103: ...in the EMAC output datapath requires that special care during the EMAC s save restore process In particular any result rounding modes must be disabled during the save restore process so the exact bit...

Page 104: ...ands yielding a signed result Multiply Unsigned mulu ea y Dx Multiplies two unsigned operands yielding an unsigned result Multiply Accumulate mac Ry RxSF ACCx msac Ry RxSF ACCx Multiplies two operands...

Page 105: ...or is available Figure 4 9 shows EMAC timing Figure 4 9 EMAC Specific OEP Sequence Stall In Figure 4 9 the OEP stalls the store accumulator instruction for three cycles the EMAC pipleline depth minus...

Page 106: ...he largest negative number that can be represented is 1 whose internal representation is 0x8000 and 0x8000_0000 respectively The largest positive word is 0x7FFF or 1 2 15 the most positive longword is...

Page 107: ...ing pseudocode explains basic MAC or MSAC instruction functionality This example is presented as a case statement covering the three basic operating modes with signed integers unsigned integers and si...

Page 108: ...duct 47 0 else result 47 0 ACCx 47 0 product 47 0 check for accumulation overflow if accumulationOverflow 1 then MACSR PAVn 1 MACSR V 1 if MACSR OMC 1 then accumulation overflow saturationMode enabled...

Page 109: ...n product 71 64 0x00 zero fill else product 71 64 8 product 63 sign extend if inst MSAC then result 47 0 ACCx 47 0 product 71 24 else result 47 0 ACCx 47 0 product 71 24 check for accumulation overflo...

Page 110: ...d result 47 0 0xffff_ffff_ffff zero fill to 48 bits before performing any scaling product 47 40 0 zero fill upper byte scale product before combining with accumulator switch SF 2 bit scale factor case...

Page 111: ...reescale Semiconductor 4 19 result 47 0 0xffff_ffff_ffff transfer the result to the accumulator ACCx 47 0 result 47 0 MACSR V MACSR PAVn MACSR N ACCx 47 if ACCx 47 0 0x0000_0000_0000 then MACSR Z 1 el...

Page 112: ...Enhanced Multiply Accumulate Unit EMAC MCF52277 Reference Manual Rev 1 4 20 Freescale Semiconductor...

Page 113: ...only the associated instruction or data line fill buffer is used For the split cache configuration one half of the tag and storage arrays is used for an instruction cache and one half is used for a d...

Page 114: ...hits in the buffer can be serviced immediately without waiting for the entire line to be fetched If the referenced address is not contained in the memory array or the associated line fill buffer the c...

Page 115: ...e registers via the BDM port For more information see Chapter 32 Debug Module Register Width bits Access2 2 Readable through debug Reset Value Section Page 0x002 Cache Control Register CACR 32 W 0x000...

Page 116: ...rol the cache configuration See the CENB definition for a detailed description 0 Enable instruction caching 1 Disable instruction caching Table 5 3 describes cache configuration and Table 5 4 describe...

Page 117: ...further decouples the write instruction and the signaling of the fault 0 Disable buffered writes 1 Enable buffered writes 7 6 Reserved must be cleared 5 DWP Default write protection 0 Read and write...

Page 118: ...pheral space 0xE000_0000 0xFFFF_FFFF should not be cached The combination of the CACR defaults and the two ACRn registers must define the non cacheable attribute for this address space Table 5 4 Cache...

Page 119: ...to references based on operating privilege mode of the ColdFire processor The field uses the ACR for user references only supervisor references only or all accesses 00 Match if user mode 01 Match if s...

Page 120: ...e cache does not monitor data references for accesses to cached instructions Therefore software must maintain instruction cache coherency by invalidating the appropriate cache entries after modifying...

Page 121: ...ress 3 2 01 fetch sequence 0x4 0x8 0xC 0x0 if miss address 3 2 10 fetch sequence 0x8 0xC 0x0 0x4 if miss address 3 2 11 fetch sequence 0xC 0x0 0x4 0x8 After an external fetch has been initiated and th...

Page 122: ...CR bits CENB and CEIB and the type of instruction fetch Table 5 7 Instruction Cache Operation as Defined by CACR CACR CENB CACR CEIB Type of Instruction Fetch Description 0 0 N A Cache is completely d...

Page 123: ...it can service processor initiated accesses or memory referencing commands from the debug module Depending on configuration information processor references may be sent to the cache and the SRAM block...

Page 124: ...e SRAM module s base address are 0x8000_0000 0x8FFE_0000 The adress must be 0 modulo 128 K Set the RAMBAR register appropriately By default the RAMBAR is invalid but the backdoor is enabled In this st...

Page 125: ...ty If a bit is cleared the SRAM backdoor has priority Priority is determined according to the following table Note The recommended setting maximum performance for the priority bits is 00 9 BDE Backdoo...

Page 126: ...ing code segment describes how to initialize the SRAM The code sets the base address of the SRAM at 0x8000_0000 and initializes the SRAM to zeros RAMBASE EQU 0x80000000 set this variable to 0x80000000...

Page 127: ...exit else continue looping 6 3 2 Power Management As noted previously depending on the RAMBAR defined configuration instruction fetch and operand read accesses may be sent to the SRAM and cache simult...

Page 128: ...Static RAM SRAM MCF52277 Reference Manual Rev 1 6 6 Freescale Semiconductor...

Page 129: ...ock the device The clock module contains Crystal amplifier and oscillator OSC Phase locked loop PLL Status and control registers Control logic NOTE Throughout this manual fsys refers to the core frequ...

Page 130: ...TDIV2 must equal the output frequency of OUTDIV1 2 2 The output frequency of OUTDIV3 must equal the output frequency of OUTDIV1 3 The output frequency of OUTDIV5 must be 60MHz if it is used as the USB...

Page 131: ...ettings See Section 7 2 1 PLL Control Register PCR for details The post VCO dividers can be enabled asynchronously or disabled via register Allows glitch free dynamic switching of the output divider P...

Page 132: ...l clock generator reference the PLL configuration must be set at reset by overriding the default reset configuration See Chapter 9 Chip Configuration Module CCM for details on setting the device for e...

Page 133: ...re are several options for enabling or disabling the PLL or crystal oscillator in stop mode compromising between stop mode current and wake up recovery time The PLL can be disabled in stop mode but re...

Page 134: ...22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PFDR 0 1 1 1 OUTDIV5 0 0 0 0 OUTDIV3 OUTDIV2 OUTDIV1 W Reset See Note 0 1 1 1 See Note 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 Note The reset valu...

Page 135: ...cluding FlexBus clock FB_CLK The divider is the value of this bit field plus one The reset value depends on the chip configuration selected See Chapter 9 Chip Configuration Module CCM for more informa...

Page 136: ...1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOL RE LOL IRQ LOCK LOCKS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 7 4 PLL Status Register PSR Table...

Page 137: ...ne count and the system is notified that the PLL has achieved frequency lock by setting the PSR LOCK bit After detection of lock the lock circuitry continues monitoring the reference and feedback freq...

Page 138: ...if an interrupt should be generated upon loss of lock In PLL bypass mode the PLL cannot lock therefore a loss of lock condition cannot occur and the LOLIRQ has no affect 7 3 4 System Clock Modes The...

Page 139: ...t is set the PLL is in frequency lock 7 3 5 2 External Reset When RESET asserts the PLL input clock outputs to the device and the PLL does not begin acquiring lock until RESET is negated The PSR LOCK...

Page 140: ...Clock Module MCF52277 Reference Manual Rev 1 7 12 Freescale Semiconductor...

Page 141: ...th bits Access Reset Value Section Page Supervisor Access Only Registers1 1 User access to supervisor only address locations have no effect and result in a bus error 0xFC04_0013 Wakeup Control Registe...

Page 142: ...D 3 The low power mode control logic processes the entry into a low power mode and the appropriate clocks usually those related to the high speed processor core are disabled 4 After entering the low p...

Page 143: ...D bits are readable and writable in all modes 00 Run 01 Doze 10 Wait 11 Stop Note If WCR LPMD is cleared the device stops executing code upon a STOP instruction However no clocks disable 3 Reserved mu...

Page 144: ...he PPMR registers provide a unique control bit for each address space that defines whether the module clock for the given space is enabled or disabled Because the operation of the crossbar switch and...

Page 145: ...0 0 Figure 8 4 Peripheral Power Management High Register PPMHR Table 8 5 PPMHR CDn Assignments Slot Number CDn Peripheral 32 CD32 PIT 0 33 CD33 PIT 1 36 CD36 PWM 37 CD37 Edge Port 40 CD40 CCM Reset C...

Page 146: ...lobal Space 2 CD2 FlexBus 8 CD8 FlexCAN 15 CD15 Real Time Clock 17 CD17 eDMA Controller 18 CD18 Interrupt Controller 0 19 CD19 Interrupt Controller 1 21 CD21 IACK 22 CD22 I2 C 23 CD23 DSPI 24 CD24 UAR...

Page 147: ...ether the system clocks are enabled upon wake up from stop mode This bit must be written before execution of the STOP instruction for it to take effect 0 System clocks enabled only when PLL is locked...

Page 148: ...e setting of the WCR LPMD bits Entry into any of these modes idles the CPU with no cycles active powers down the system and stops all internal clocks appropriately During stop mode the system clock is...

Page 149: ...3 4 Peripheral Behavior in Low Power Modes The functionality of each of the peripherals and CPU during the various low power modes is summarized in Table 8 9 and detailed in the following sections In...

Page 150: ...am N A Stopped N A SSI Enabled Interrupt Enabled Interrupt Stopped N A Real Time Clock Enabled Interrupt Enabled Interrupt Enabled Interrupt Programmable Interrupt Timers Enabled Interrupt Program Int...

Page 151: ...explained in Section 8 2 5 Low Power Control Register LPCR 8 3 4 4 Chip Configuration Module The chip configuration module is unaffected by entry into a low power mode If a reset exits low power mode...

Page 152: ...he interrupt priority mask field of the CPU s status register SR and above the level programmed in the WCR PRILVL The interrupt must also be enabled in the interrupt controller s interrupt mask regist...

Page 153: ...stored in or attempt to access SDRAM 8 3 4 14 USB On the Go Module If the USB On the Go module is clocked externally it operates normally in wait mode It is capable of generating an interrupt to wake...

Page 154: ...Tx pins as recessive FlexCAN loses synchronization with the CAN bus and the CANMCR STOP_ACK NOT_RDY bits are set Exiting stop mode is done in one of the following ways Reset the FlexCAN by hard reset...

Page 155: ...errupt to exit the low power modes 8 3 4 21 DMA Timers DTIM0 3 In wait and doze modes the DMA timers may generate an interrupt to exit a low power mode This interrupt can generate when the DMA timer i...

Page 156: ...enerates the interrupt signal to the CPU and interrupt controller The setting of I2SR IIF signifies the completion of one byte transfer or the reception of a calling address matching its own specified...

Page 157: ...Facilitates serial boot See Chapter 10 Serial Boot Facility SBF for details 9 1 3 Modes of Operation The only chip operating mode available on this device is master mode In master mode the ColdFire c...

Page 158: ...tion The CCM programming model consists of the registers listed in the below table Table 9 1 Signal Properties Name Direction Description Reset State BOOTMOD 1 0 I Reset configuration select FB_A 21 1...

Page 159: ...r Status Register UOCSR 16 R W 0x3010 9 3 6 9 8 0xFC0A_0018 Serial Boot Facility Status Register SBFSR 2 16 R See Section 10 3 1 10 2 0xFC0A_001A Serial Boot Facility Control Register SBFCR 2 16 R W S...

Page 160: ...1 16 1 D 31 0 SDRAM SDR data 31 0 or FlexBus data 31 0 7 6 CSC Chip select configuration Reflects the chosen chip select configuration 00 FB_A 23 22 FB_A 23 22 01 FB_A 23 22 FB_CS5 A22 10 FB_A 23 22 F...

Page 161: ...upervisor read only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PIN PRN W Reset Device Dependent Mask Set Dependent Figure 9 4 Chip Identification Register CIR Table 9 5 CIR Field Descriptions Field Descr...

Page 162: ...is used 13 USBPUE USB transceiver pull up enable Enables the on chip USB OTG controller to drive the internal transceiver pull up 0 Internal transceiver pull up is disabled 1 USB OTG drives the intern...

Page 163: ...DMA Timer DMA mux selection Selects between the timer DMA signals and SSI DMA signals as those signals are mapped to DMA channels 9 12 Refer to the Chapter 17 Enhanced Direct Memory Access eDMA for mo...

Page 164: ...on 15 12 Reserved must be cleared 11 8 LPDIV Low power clock divider Specifies the divide value used to produce the system clocks during limp mode A 2 1 ratio is maintained between the core and the in...

Page 165: ...valid Indicates if the session for an A peripheral is valid 0 Session is not valid for an A peripheral 1 Session is valid for an A peripheral 6 BVLD B peripheral is valid Indicates if the session for...

Page 166: ...ule configuration NOTE The logic levels for reset configuration on FB_A 21 16 must be actively driven when BOOTMOD equals 10 The FB_A 23 22 15 0 pins must be allowed to float or be pulled high Table 9...

Page 167: ...16 pins is possible only if the external BOOTMOD 1 0 pins are 10 while RSTOUT is asserted 2 The FB_A 23 22 15 0 pins do not affect reset configuration 3 The external reset override circuitry drives th...

Page 168: ...als mapped to DMA channels 9 12 respectively 1 SSI RX0 SSI RX1 SSI TX0 SSI TX1 DMA signals mapped to DMA channels 9 12 respectively none MISCCR 2 LCDCHEN 22 LCD Internal Clock Enable 0 LCD internal cl...

Page 169: ...SSI_TXD pull cells enabled U1TXD SSI_TXD U1RXD SSI_RXD MISCCR 6 SSIPUS 13 SSI RXD TXD Pull Select 0 SSI_RXD SSI_TXD pulled low 1 SSI_RXD SSI_TXD pulled high SSI_CLKIN MISCCR 4 SSISRC 12 SSI Clock Sou...

Page 170: ...as shown in Table 9 13 After reset is exited the output pad strength configuration can only be changed using the GPIO module For more information see Chapter 14 General Purpose I O Module 9 4 4 Chip S...

Page 171: ...scale Semiconductor 9 15 9 4 5 Low Power Configuration After reset the device can be configured for operation during the low power modes using the low power control register LPCR For more information...

Page 172: ...Chip Configuration Module CCM MCF52277 Reference Manual Rev 1 9 16 Freescale Semiconductor...

Page 173: ...pins Figure 10 1 SBF Block Diagram 10 1 1 Overview The SBF interfaces to an external SPI memory to read configuration data and boot code during the processor reset sequence if BOOTMOD 1 0 equals 11 B...

Page 174: ...FSR The read only SBFSR register reflects the amount of boot code loaded through the external SPI memory Table 10 1 Signal Properties Signal I O Description Reset Pull Up SBF_CK O Shift clock Alternat...

Page 175: ...10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 FR BLDIV W Reset 0 0 0 0 0 0 0 0 0 0 0 01 See Note 1 Reset value is 0 and is reset only by power on reset remains unchanged for other reset types Note T...

Page 176: ...oot loader clock divider Determines the SBF clock PLL input reference clock divisor that generates the serial shift clock output on SBF_CK Prior to the serial boot sequence a divisor of 67 is used Dur...

Page 177: ...benefit from the optional FAST_READ on soft reset feature e g the SPI memory does not support FAST_READ or the input reference clock does not exceed the maximum allowable frequency for the READ comma...

Page 178: ...initial stack pointer and program counter should point to locations in the on chip SRAM so that boot code can initialize the device and load the application software from the SPI memory or via some o...

Page 179: ...e that sets the SBFCR BLDIV field The value written to SBFCR BLDIV should correspond to the frequency the SPI memory supports in FAST_READ mode After a soft reset SBFCR BLDIV is not overwritten with t...

Page 180: ...Serial Boot Facility SBF MCF52277 Reference Manual Rev 1 10 8 Freescale Semiconductor...

Page 181: ...t controller and is explained in these Figure 11 1 Reset Controller Block Diagram 11 1 2 Features Module features include the following Five sources of reset External Power on reset POR Core watchdog...

Page 182: ...er on RESET When RSTOUT is active the user can drive override options on the data bus See Chapter 9 Chip Configuration Module CCM for more details on these override options 11 3 Memory Map Register De...

Page 183: ...ad at any time Writing to RSR has no effect Address 0xFC0A_0000 RCR Access User read write 7 6 5 4 3 2 1 0 R SOFTRST FRCRSTOUT 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Figure 11 2 Reset Control Register RC...

Page 184: ...ware 1 Last reset caused by software 4 Reserved must be cleared 3 POR Power on reset flag Indicates power on reset caused the last reset 0 Last reset not caused by power on reset 1 Last reset caused b...

Page 185: ...n stop mode causes an external reset to be recognized asynchronously 11 4 1 3 Core Watchdog Timer Reset A core watchdog timer timeout causes the timer reset request to be recognized and latched If the...

Page 186: ...in Figure 11 4 All cycle counts given are approximate N RESET Pin or WD Timeout or SW Reset Loss Of Lock RESET Negated BOOTMOD 1 0 10 PLL Locked Assert RSTOUT and Latch Reset Status Wait 512 FB_CLK Cy...

Page 187: ...trol logic waits for the PLL to attain lock 7 before waiting 512 bus clock cycles 10 or for the duration of serial boot 9 For non serial boot the reset control logic may then latch the chip configurat...

Page 188: ...Reset Controller Module MCF52277 Reference Manual Rev 1 11 8 Freescale Semiconductor...

Page 189: ...s core watchdog timer CWT provides a means of preventing system lockup due to uncontrolled software loops via a special software service sequence If periodic software servicing action does not occur...

Page 190: ...32 R W 0x4444_4444 12 2 2 12 3 0xFC00_0028 Peripheral Access Control Register C PACRC 32 R W 0x4444_4444 12 2 2 12 3 0xFC00_002C Peripheral Access Control Register D PACRD 32 R W 0x4444_4444 12 2 2 1...

Page 191: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Figure 12 1 Master Privilege Register MPR Table 12 2 MPROTn Assignments Crossbar Switch Port Number MPROTn Master M0 MPROT0 ColdFire Core M1 MPROT1 eDM...

Page 192: ...0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 Figure 12 4 Peripheral Access Control Register B PACRB Address 0xFC00_0028 PACRC Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 193: ...Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 Figure 12 9 Peripheral Access Control Register G PACRG Address 0xFC00_0050 PACRI Access User read write 31 30 29 28 27 26 25 24 23...

Page 194: ...Global Space 1 PACR65 Global Space 2 3 2 1 0 R 0 SP WP TP W Figure 12 11 PACRn Fields Table 12 5 PACRn Field Descriptions Field Description 3 Reserved must be cleared 2 SP Supervisor protect Determin...

Page 195: ...Access User read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RO 0 0 0 0 0 CW CIN16 CW RWH CWE CWRI CWT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12 12 Core Watchdog Control Register CWCR Table...

Page 196: ...he SCMISR 6 5 CWRI Core watchdog reset interrupt 00 If a time out occurs the CWT generates an interrupt to the core Refer to Chapter 15 Interrupt Controller Modules for details on setting its priority...

Page 197: ...must be cleared 1 CFEI Core fault error interrupt flag Indicates if a bus fault has occurred Writing a 1 clears this bit and negates the interrupt request Writing a 0 has no effect 0 No bus error 1 A...

Page 198: ...burst enable for reads Allows bursts to happen on read transactions from the crossbar switch slaves to the USB On the Go module 0 Read bursts are disabled 1 Read bursts are enabled Note If GBR and GBW...

Page 199: ...0 0 0 0 0 Figure 12 17 Core Fault Interrupt Enable Register CFIER Table 12 10 CFIER Field Descriptions Field Description 7 1 Reserved must be cleared 0 ECFEI Enable core fault error interrupt 0 Do not...

Page 200: ...s faults This register can only be read any attempted write is ignored Address 0xFC04_0077 CFATR Access User read only 7 6 5 4 3 2 1 0 R WRITE SIZE 0 0 MODE TYPE W Reset Figure 12 19 Core Fault Attrib...

Page 201: ...mes trapped in a loop with no controlled exit or if a bus transaction becomes hung The core watchdog timer can be enabled through CWCR CWE it is disabled at reset If enabled the CWT requires the perio...

Page 202: ...uration After this bit CWCR RO is set a system reset is required to clear it For certain values in the CWCR CWRI field the CWT generates an interrupt response to a time out For these configurations th...

Page 203: ...n methods and attributes may be programmed on a slave by slave basis The MCF5227x devices have up to five masters and three slaves 5Mx3S connected to the crossbar switch The five masters are the ColdF...

Page 204: ...fies the cacheable space 13 2 Features The crossbar switch includes these distinctive features Symmetric crossbar bus switch implementation Allows concurrent accesses from different masters to differe...

Page 205: ...visor mode Additionally these registers can only be read from or written to by 32 bit accesses A bus error response is returned if an unimplemented location is accessed within the crossbar switch See...

Page 206: ...Slave n XBS_PRSn Table 13 3 XBS_PRSn Field Descriptions Field Description 31 Reserved must be cleared 30 28 M7 Master 7 Serial Boot priority This field sets the arbitration priority for this port on t...

Page 207: ...RSn Field Descriptions Field Description 31 RO Read only Forces both of the slave port s registers XBS_CRSn and XBS_PRSn to be read only After set onlya hardware reset clears it 0 Both of the slave po...

Page 208: ...riority level is higher than that of the master that currently has control of the slave port the new requesting master is granted control over the slave port at the next clock edge The exception to th...

Page 209: ...in line is granted access to the slave port at the next transfer boundary Parking may continue to be used in a round robin mode but does not affect the round robin pointer unless the parked master ac...

Page 210: ...Crossbar Switch XBS MCF52277 Reference Manual Rev 1 13 8 Freescale Semiconductor...

Page 211: ...sed for their primary function many of the pins may be used as general purpose digital I O GPIO pins In some cases the pin function is set by the operating mode and the alternate pin functions are not...

Page 212: ...RTS USB_VBUS_OC T1IN PUART2 U0RXD CANRX PUART1 U0TXD CANTX PUART0 T3IN T3OUT SSI_MCLK PTIMER3 T2IN T2OUT DSPI_PCS2 PTIMER2 T1IN T1OUT LCD_CONTRAST PTIMER1 Internal Bus Drive Strength Control FB_TS DAC...

Page 213: ...pins and other pins not controlled by the ports module The function of most of the pins primary function GPIO etc is determined by the ports module pin assignment registers PAR_x NOTE In this table a...

Page 214: ...D 141 139 137 135 A12 B12 C12 B13 A13 A14 FB_A 15 14 SD_BA 1 0 O SDVDD 131 130 B14 C13 FB_A 13 11 SD_A 13 11 O SDVDD 129 127 C14 D12 D13 FB_A10 O SDVDD 126 D14 FB_A 9 0 SD_A 9 0 O SDVDD 125 116 E11 E1...

Page 215: ...CD_D 17 16 6 PLCDDH 1 0 LCD_D 11 10 O EVDD 9 8 E3 E4 LCD_D 15 14 6 PLCDDM 7 6 LCD_D 9 8 O EVDD 7 6 D1 D2 LCD_D13 PLCDDM5 CANTX O EVDD C1 LCD_D12 PLCDDM4 CANRX O EVDD C2 LCD_D 11 8 6 PLCDDM 3 0 LCD_D 7...

Page 216: ...U2RXD U I O EVDD 167 D5 DSPI7 DSPI_PCS0 SS PDSPI3 U2RTS U I O EVDD 152 B9 DSPI_SIN PDSPI2 U2RXD SBF_DI 8 I EVDD 155 D8 DSPI_SOUT PDSPI1 U2TXD SBF_D0 O EVDD 154 D9 DSPI_SCK PDSPI0 U2CTS SBF_CK I O EVD...

Page 217: ...LPST O EVDD 76 JTAG_EN D I EVDD 79 K10 PSTCLK TCLK U O EVDD 74 P8 DSI TDI U I EVDD 78 M11 DSO TDO O EVDD 81 L11 BKPT TMS U I EVDD 80 N11 DSCLK TRST U I EVDD 77 P11 Test TEST D I EVDD 134 E10 Power Sup...

Page 218: ...etermined by the edge port module The GPIO module is only responsible for assigning the alternate functions 5 Pull up when DREQ controls the pin 6 The 176 LQFP device only supports a 12 bit LCD data b...

Page 219: ...x03 14 3 1 14 11 0xFC0A_400A PODR_LCDDATAM 8 R W 0xFF 14 3 1 14 11 0xFC0A_400B PODR_LCDDATAL 8 R W 0xFF 14 3 1 14 11 Port Data Direction Registers 0xFC0A_400C PDDR_BE 8 R W 0x00 14 3 2 14 12 0xFC0A_40...

Page 220: ...C0A_402A PCLRR_DSPI 8 W 0x00 14 3 4 14 15 0xFC0A_402B PCLRR_TIMER 8 W 0x00 14 3 4 14 15 0xFC0A_402C PCLRR_LCDCTL 8 W 0x00 14 3 4 14 15 0xFC0A_402D PCLRR_LCDDATAH 8 W 0x00 14 3 4 14 15 0xFC0A_402E PCLR...

Page 221: ...x register clear the PODR_x bits or clear the corresponding bits in the PCLRR_x register Mode Select Control Registers 0xFC0A_4044 MSCR_FLEXBUS 8 R W 0x3F 14 3 6 14 23 0xFC0A_4045 MSCR_SDRAM 8 R W 0x3...

Page 222: ...DR_x register configures the corresponding pin as an input Address 0xFC0A_4000 PODR_BE 0xFC0A_4001 PODR_CS 0xFC0A_4002 PODR_FBCTL 0xFC0A_4006 PODR_DSPI 0xFC0A_4007 PODR_TIMER 0xFC0A_4008 PODR_LCDCTL A...

Page 223: ...DR_x W Reset 0 0 0 0 0 0 0 0 Figure 14 5 Port Data Direction Registers PDDR_x Address 0xFC0A_400C PDDR_BE 0xFC0A_400D PDDR_CS 0xFC0A_400E PDDR_FBCTL 0xFC0A_4012 PDDR_DSPI 0xFC0A_4013 PDDR_TIMER 0xFC0A...

Page 224: ...ata Registers PPDSDR_x Address 0xFC0A_4018 PPDSDR_BE 0xFC0A_4019 PPDSDR_CS 0xFC0A_401A PPDSDR_FBCTL 0xFC0A_401E PPDSDR_DSPI 0xFC0A_401F PPDSDR_TIMER 0xFC0A_4020 PPDSDR_LCDCTL Access User read write 7...

Page 225: ...0 0 0 0 0 W PCLRR_x Reset 0 0 0 0 0 0 0 0 Figure 14 11 Port Clear Output Data Registers PCLRR_x Address 0xFC0A_4024 PCLRR_BE 0xFC0A_4025 PCLRR_CS 0xFC0A_4026 PCLRR_FBCTL 0xFC0A_402A PCLRR_DSPI 0xFC0A_...

Page 226: ...write 7 6 5 4 3 2 1 0 R 0 0 0 0 PAR_BE3 PAR_BE2 PAR_BE1 PAR_BE0 W Reset 0 0 0 0 1 1 1 1 Figure 14 14 Byte Enable Pin Assignment Register PAR_BE Table 14 9 PAR_BE Field Descriptions Field Description...

Page 227: ...00 FB_CS1 pin configured for GPIO 01 Reserved 10 FB_CS1 pin configured for SD_CS1 11 FB_CS1 pin configured for FlexBus chip select 1 function 3 PAR_CS0 FB_CS0 pin assignment 0 FB_CS0 pin configured f...

Page 228: ..._I2C Table 14 12 PAR_I2C Field Descriptions Field Description 7 4 Reserved must be cleared 3 2 PAR_SCL I2C_SCL pin assignment 00 I2C_SCL pin configured for GPIO 01 I2C_SCL pin configured for UART2 tra...

Page 229: ...write 7 6 5 4 3 2 1 0 R PAR_PCS0 PAR_SIN PAR_SOUT PAR_SCK W Reset 0 0 0 0 0 0 0 0 Figure 14 19 DSPI Pin Assignment Register PAR_DSPI Table 14 14 PAR_DSPI Field Descriptions Field Description 7 6 PAR_...

Page 230: ...R_T2IN 3 2 PAR_T1IN 1 0 PAR_T0IN DMA timer pin assignment These bit fields configure the DMA timer pins for one of their primary functions or GPIO Address 0xFC0A_4038 PAR_LCDCTL Access User read write...

Page 231: ...ad write 7 6 5 4 3 2 1 0 R 0 0 0 0 PAR_IRQ4 PAR_IRQ1 W Reset 0 0 0 0 0 0 0 0 Figure 14 22 IRQ Pin Assignment PAR_IRQ Table 14 17 PAR_IRQ Field Descriptions Field Description 7 4 Reserved must be clear...

Page 232: ...scriptions Field Description 31 12 Reserved must be cleared 11 10 PAR_LD17 9 8 PAR_LD16 7 6 PAR_LD17 5 4 PAR_LD14 3 2 PAR_LD13 1 0 PAR_LD12 LCD data pin assignment These bit fields configure the LCD d...

Page 233: ...e the LCD data pins for one of their primary functions or GPIO 7 0 Reserved must be cleared Address 0xFC0A_4044 MSCR_FLEXBUS Access User read write 7 6 5 4 3 2 1 0 R 0 0 MSCR_DUPPER MSCR_DLOWER MSCR_A...

Page 234: ...Half strength 1 8V low power mobile DDR 01 Open drain 10 Full strength 1 8V low power mobile DDR 11 2 5V DDR1 or 3 3V CMOS with roughly equal rise and fall delays 1 0 MSCR_ ADDRCTL FB_A 23 0 BE BWE 3...

Page 235: ...0 Half strength 1 8V low power mobile DDR 01 Open drain 10 Full strength 1 8V low power mobile DDR 11 2 5V DDR1 or 3 3V CMOS with roughly equal rise and fall delays Address 0xFC0A_4048 DSCR_DSPI 0xFC0...

Page 236: ...l Register DSCR_UART Table 14 22 DSCR_x Field Descriptions Field Description DSCR_x Drive strength control Controls the drive strength of the various pins See Table 14 23 for a list of the pins affect...

Page 237: ...a PPDSDR_x register returns the current state of the corresponding pins when configured as general purpose I O regardless of whether the pins are inputs or outputs Every GPIO port has a PPDSDR_x regi...

Page 238: ...miconductor 14 5 Initialization Application Information The initialization for the ports module is done during reset configuration All registers are reset to a predetermined state Refer to Section 14...

Page 239: ...ily is appropriate The interrupt architecture of ColdFire is exactly the same as the M68000 family where there is a 3 bit encoded interrupt priority level sent from the interrupt controller to the cor...

Page 240: ...fferent than previous 68K ColdFire cores In this approach all IACK cycles are directly managed by the interrupt controller so the requesting peripheral device is not accessed during the IACK As a resu...

Page 241: ...0xFC04_8040 n n 0 63 Interrupt Control Registers ICR0n 8 R W 0x00 15 2 9 15 11 0xFC04_80E0 Software Interrupt Acknowledge SWIACK0 8 R 0x00 15 2 10 15 14 0xFC04_80E0 4n n 1 7 Level n Interrupt Acknowl...

Page 242: ...INT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 15 1 Interrupt Pending Register High IPRHn Table 15 3 IPRHn Field Descriptions Field Description 31 0 INT Interrupt...

Page 243: ...els 1 6 first write a higher level interrupt mask to the status register before setting the mask in the IMR or the module s interrupt mask register After the mask is set return the interrupt mask in t...

Page 244: ...te an interrupt The corresponding IPRHn bit reflects the state of the interrupt signal even if the corresponding IMRHn bit is set 0 The corresponding interrupt source is not masked 1 The corresponding...

Page 245: ...NTFRCLn Field Descriptions Field Description 31 0 INTFRCL Interrupt force Allows software generation of interrupts for each possible source for functional or debug purposes 0 No interrupt forced on co...

Page 246: ...roller automatically loads the level of an interrupt request into the CLMASK current level mask when the acknowledge is performed At the exact same cycle the value of the current interrupt level mask...

Page 247: ...ssertion of the interrupt signal to the processor core As the CLMASK register is updated during the IACK cycle read the former value is saved in the SLMASK register Typically after a level n interrupt...

Page 248: ...after a level n interrupt request is managed the service routine restores the saved level mask value into the current level mask register to re enable the lower priority requests NOTE Only one copy o...

Page 249: ...the ColdFire processor Address 0xFC04_801F SLMASK Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 SLMASK W Reset 0 0 0 0 1 1 1 1 Figure 15 11 Saved Level Mask Register SLMASK Table 15 13 SLMASK Fiel...

Page 250: ...er complete Write EDMA_CINTR CINT 5 14 EDMA_INTR INT06 DMA Channel 6 transfer complete Write EDMA_CINTR CINT 6 15 EDMA_INTR INT07 DMA Channel 7 transfer complete Write EDMA_CINTR CINT 7 16 EDMA_INTR I...

Page 251: ...rupt Write 1 to BUF0I after reading as 1 5 BUF1I Message Buffer 1 Interrupt Write 1 to BUF1I after reading as 1 6 BUF2I Message Buffer 2 Interrupt Write 1 to BUF2I after reading as 1 7 BUF3I Message B...

Page 252: ...ag Write PIF 1 or write PMR 44 PIT1 PCSR1 PIF PIT interrupt flag Write PIF 1 or write PMR 45 Not Used 46 Not Used 47 USB OTG USB_STS USB OTG interrupt Write 1 to corresponding bit in the USB_STS 48 No...

Page 253: ...o active requests returns a value of 24 0x18 signaling a spurious interrupt In addition to the software IACK registers in each interrupt controller there are global software IACK registers A read from...

Page 254: ...equest sources IPRn and the interrupt mask register IMRn to determine if there are active requests This is the recognition phase The interrupt force register INTFRCn also factors into the generation o...

Page 255: ...le because the interrupt controller completely services the acknowledge This means the interrupt source must be explicitly disabled in the interrupt service routine This design provides unique vector...

Page 256: ...ogic path which evaluates any unmasked interrupt requests The device waits for an event to generate a level 7 interrupt request or an interrupt request with a priority level greater than the value pro...

Page 257: ...the beginning of segment C During C the initial portion of the ISR executes Near the end of this segment the ISR accesses the peripheral to negate the interrupt request source At the conclusion of se...

Page 258: ...nd incur the overhead of another interrupt exception At the conclusion of segment G the processor core returns to the original interrupted task or a different task ready to execute Obviously there are...

Page 259: ...put output I O pin NOTE Not all EPORT signals may be output from the device See Chapter 2 Signal Descriptions to determine which signals are available Figure 16 1 EPORT Block Diagram NOTE The GPIO mod...

Page 260: ...is bypassed for the level detect logic because no clocks are available 16 3 Interrupt GPIO Pin Descriptions All EPORT pins default to general purpose input pins at reset The pin value is synchronized...

Page 261: ...ions have no effect and result in a bus error 0xFC09_4000 EPORT Pin Assignment Register EPPAR 16 R W 0x0000 16 4 1 16 3 0xFC09_4002 EPORT Data Direction Register EPDDR 8 R W 0x00 16 4 2 16 4 0xFC09_40...

Page 262: ...iguration as input or output Interrupt requests generated in the EPORT module can be masked by the interrupt controller module EPPAR functionality is independent of the selected pin direction Reset cl...

Page 263: ...rresponding bit in the EPORT flag register EPFR is set or later becomes set The corresponding pin level is low and the pin is configured for level sensitive operation Clearing a bit in EPIER negates a...

Page 264: ...he write cycle terminates normally Reset does not affect EPPDR 0 Reserved must be cleared Address 0xFC09_4006 EPFR Access User read write 7 6 5 4 3 2 1 0 R EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 0 W Reset...

Page 265: ...at performs source and destination address calculations and the actual data movement operations along with local memory containing transfer control descriptors for each channel 17 2 Block Diagram Figu...

Page 266: ...fer count An outer data transfer loop defined by a major iteration count Channel activation via one of three methods Explicit software initiation Initiation via a channel to channel linking mechanism...

Page 267: ...equests are needed the DREQn signal must negate after the DACKn assertion and on or before the second cycle following the data phase of the last internal bus write see Figure 17 2 If another service r...

Page 268: ...through without regard to priority Table 17 2 eDMA Controller Memory Map Address Register Width bits Access Reset Value Section Page 0xFC04_4000 eDMA Control Register EDMA_CR 32 R W 0x0000_0000 17 6...

Page 269: ...r size boundaries The minor loop byte count must be a multiple of the source and destination transfer sizes All source reads and destination writes must be configured to the natural boundary of the pr...

Page 270: ...t When a system bus error occurs the channel terminates after the read or write transaction which is already pipelined after errant access has completed If a bus error occurs on the last read prior to...

Page 271: ...destination address configuration error 1 The last recorded error was a configuration error detected in the TCDn_DADDR field TCDn_DADDR is inconsistent with TCDn_ATTR DSIZE 4 DOE Destination offset e...

Page 272: ...request The assignments between the DMA requests from the peripherals to the channels of the eDMA are shown in Table 17 6 Address 0xFC04_400E EDMA_ERQ Access User read write 15 14 13 12 11 10 9 8 7 6...

Page 273: ...write sequence to the EDMA_EEI register The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt...

Page 274: ...lue on a register write causes the corresponding bit in the EDMA_ERQ to be cleared Setting the CAER bit provides a global clear function forcing the entire contents of the EDMA_ERQ to be cleared disab...

Page 275: ...DMA_EEI to be cleared Setting the CAEE bit provides a global clear function forcing the EDMA_EEI contents to be cleared disabling all DMA request inputs Reads of this register return all zeroes Table...

Page 276: ...7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 W CAEE CEEI Reset 0 0 0 0 0 0 0 0 Figure 17 10 eDMA Clear Enable Error Interrupt Register EDMA_CEEI Table 17 11 EDMA_CEEI Field Descriptions Field Description 7 Reserved...

Page 277: ...ven channel The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set Setting the SAST bit provides a global set function forcing all START bit...

Page 278: ...t START Bit Register EDMA_SSRT Table 17 14 EDMA_SSRT Field Descriptions Field Description 7 Reserved must be cleared 6 SAST Set all START bits activates all channels 0 Set only those TCDn_CSR START bi...

Page 279: ...s register The outputs of this register are enabled by the contents of the EDMA_EEI and then routed to the interrupt controller During the execution of the interrupt service routine associated with an...

Page 280: ...write sequence it is again eligible for preemption If any higher priority channel is requesting service the restored channel is suspended and the higher priority channel is serviced Nested preemption...

Page 281: ...itration priority Channel priority when fixed priority arbitration is enabled Table 17 19 TCDn Memory Structure eDMA Offset TCDn Register Name Abbreviation Width bits 0xFC04_5000 0x20 n Source Address...

Page 282: ...ly For data queues requiring power of 2 size bytes the queue should start at a 0 modulo size address and the SMOD field should be set to the appropriate value for the queue freezing the desired number...

Page 283: ...stalled by using the bandwidth control field or via preemption After the minor count is exhausted the SADDR and DADDR values are written back into the TCD memory the major iteration count is decremen...

Page 284: ...el linking is disabled 1 The channel to channel linking is enabled Note This bit must be equal to the BITER E_LINK bit Otherwise a configuration error is reported 14 13 Reserved must be cleared 12 9 L...

Page 285: ...iptions Field Description 31 0 DLAST_SGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel scatter gather If TCDn_CSR E_...

Page 286: ...inor loop is exhausted the eDMA engine initiates a channel service request at the channel defined by these four bits by setting that channel s TCDn_CSR START bit 0 15 Link to DMA channel 0 15 Note Whe...

Page 287: ...6 ACTIVE Channel active This flag signals the channel is currently in execution It is set when channel service begins and the eDMA clears it as the minor loop completes or if any error condition is d...

Page 288: ...writes the new values for the TCDn_ SADDR DADDR CITER back to local memory If the major iteration count is exhausted additional processing are performed including the final address pointer updates re...

Page 289: ...nd the destination is 32 bit data two reads are performed then one 32 bit write Transfer Control Descriptor Memory Memory Controller This logic implements the required dual ported controller managing...

Page 290: ...l data movement The source reads are initiated and the fetched data is temporarily stored in the data path block until it is gated onto the internal bus during the destination write This source read d...

Page 291: ...de the final address adjustments and reloading of the BITER field into the CITER Assertion of an optional interrupt request also occurs at this time as does a possible fetch of a new TCD from memory u...

Page 292: ...ther than the default is desired 3 Enable error interrupts in the EDMA_EEI if so desired 4 Write the 32 byte TCD for each channel that may request service 5 Enable any hardware service requests via th...

Page 293: ...st processing executes interrupts major loop channel linking and scatter gather operations if enabled Table 17 32 shows how each DMA request initiates one minor loop transfer iteration without CPU int...

Page 294: ...eescale Semiconductor Table 17 33 lists the memory array terms and how the TCD settings interrelate Table 17 32 Example of Multiple Loop Iterations Current Major Loop Iteration Count CITER DMA Request...

Page 295: ...owest numbered channel with that priority is selected by arbitration and executed by the eDMA engine The hardware service request handshake signals error interrupts and error reporting is associated w...

Page 296: ...0 The destination memory has a longword wide port located at 0x2000 The address offsets are programmed in increments to match the transfer size one byte for the source and four bytes for the destinati...

Page 297: ...t example is the same as previous The only fields that change are the major loop iteration count and the final address offsets The eDMA is programmed for two iterations of the major loop transferring...

Page 298: ...om 0x1017 d Write longword to location 0x2014 second iteration of the minor loop e Read byte from location 0x1018 read byte from location 0x1019 read byte from 0x101A read byte from 0x101B f Write lon...

Page 299: ...Dn_CSR START was set Polling the TCDn_CSR ACTIVE bit may be inconclusive because the active status may be missed if the channel execution is short in duration The TCD status bits execute the following...

Page 300: ...ely running relative priority outstanding requests become undefined Channel priorities are treated as equal constantly rotating when round robin arbitration mode is selected The TCDn_CSR ACTIVE bit fo...

Page 301: ...NOTE The TCDn_CITER E_LINK bit and the TCDn_BITER E_LINK bit must equal or a configuration error is reported The CITER and BITER vector widths must be equal to calculate the major loop half way done i...

Page 302: ...ommended when executing a dynamic channel link or dynamic scatter gather request 1 Set the TCDn_CSR MAJOR_E_LINK bit 2 Read back the TCDn_CSR MAJOR_E_LINK bit 3 Test the TCDn_CSR MAJOR_E_LINK request...

Page 303: ...xBus data bus FB_D 31 16 This chapter only uses FB_D 31 0 or FB_D 31 X to designate the data bus but the actual pins used depend on the setting Take this into consideration throughout this chapter 18...

Page 304: ...of byte lanes carrying the data is determined by the port size associated with the matching chip select Because this device shares the FlexBus signals with the SDRAM controller these signals tristate...

Page 305: ...s driven high during read bus cycles and low during write bus cycles Because this device shares the FlexBus signals with the SDRAM controller this signal tristates between bus cycles 18 2 6 Transfer S...

Page 306: ...unused or reserved locations terminates normally and returns zeros 18 3 1 Chip Select Address Registers CSAR0 CSAR5 The CSARn registers specify the chip select base addresses NOTE Because the FlexBus...

Page 307: ...0 0 0 0 0 0 0 0 0 Figure 18 1 Chip Select Address Registers CSARn Table 18 3 CSARn Field Descriptions Field Description 31 16 BA Base address Defines the base address for memory dedicated to chip sel...

Page 308: ...FFF and one from 0x8_0000 0x8_FFFF Likewise for FB_CS0 to access 32 Mbytes of address space starting at location 0x0 FB_CS1 must begin at the next byte after FB_CS0 for a 16 Mbyte address space Then C...

Page 309: ...ct Control Registers CSCRn Table 18 5 CSCRn Field Descriptions Field Description 31 26 SWS Secondary wait states The number of wait states inserted before an internal transfer acknowledge is generated...

Page 310: ...s and before an internal transfer acknowledge is generated WS 0 inserts zero wait states WS 0x3F inserts 63 wait states If AA is reserved FB_TA must be asserted by the external system regardless of th...

Page 311: ..._D 31 16 if SBM 0 or FB_D 15 0 if SBM 1 5 BEM Byte enable mode Specifies the byte enable operation Certain memories have byte enables that must be asserted during reads and writes BEM can be set in th...

Page 312: ...m other external chip select outputs after system reset After system reset FB_CS0 is asserted for every external access No other chip select can be used until the valid bit CSMR0 V is set at which poi...

Page 313: ...ort requires one transfer on each four byte lane of the FlexBus Figure 18 4 Connections for External Memory Port Sizes CSCRn SBM 0 18 4 4 Bus Cycle Execution As shown in Figure 18 7 and Figure 18 9 ba...

Page 314: ...on the rising edge of FB_CLK and FB_CSn is asserted Data is driven on FB_D 31 X for writes and FB_D 31 X is tristated for reads Address continues to be driven on FB_A 0 pins If FB_TA is recognized as...

Page 315: ...ly terminated bus cycles NOTE The processor drives the data lines during the first clock cycle of the transfer with the full 32 bit address This may be ignored by standard connected devices using non...

Page 316: ...FB_R W S0 S1 S2 DATA FB_TS FB_A 23 0 ADDR 23 0 FB_D 31 X ADDR 31 X FB_CSn FB_OE FB_BE BWEn FB_TA S0 S3 1 Select the appropriate slave device Assert FB_TA external termination 3 1 Negate FB_TA external...

Page 317: ...scenarios Figure 18 10 illustrates the basic byte read transfer to an 8 bit device with no wait states The address is driven on the FB_A bus throughout the bus cycle The external device returns the re...

Page 318: ...wait states The address is driven on the FB_A 0 bus throughout the bus cycle The external device returns the read data on FB_D 31 16 and may tristate the data line or continue driving the data one clo...

Page 319: ...FB_D 31 16 Figure 18 13 Single Word Write Transfer Figure 18 14 depicts a longword read through a 32 bit device Figure 18 14 Longword Read Transfer FB_CLK S0 S1 S2 S3 FB_D 31 16 FB_R W FB_TS FB_TA FB_...

Page 320: ...teristics of a basic read or write bus cycle to provide additional address setup address hold and time for a device to provide or latch data 18 4 5 4 1 Wait States Wait states can be inserted before e...

Page 321: ...d Figure 18 12 with the default of no wait states Figure 18 16 Basic Read Bus Cycle No Wait States Figure 18 17 Basic Write Bus Cycle No Wait States FB_CLK FB_R W FB_TS S0 S1 S2 S3 DATA FB_A 23 0 ADDR...

Page 322: ...e 18 18 Read Bus Cycle One Wait State Figure 18 19 Write Bus Cycle One Wait State 18 4 5 4 2 Address Setup and Hold The timing of the assertion and negation of the chip selects byte selects and output...

Page 323: ...ddress setup Figure 18 20 Read Bus Cycle with Two Clock Address Setup No Wait States Figure 18 21 Write Bus Cycle with Two Clock Address Setup No Wait States FB_CLK FB_R W FB_TS S0 AS S1 S2 S3 DATA FB...

Page 324: ...e negate Figure 18 22 and Figure 18 23 show read and write bus cycles with two clocks of address hold Figure 18 22 Read Cycle with Two Clock Address Hold No Wait States Figure 18 23 Write Cycle with T...

Page 325: ...sult of such transfer translations The FlexBus can support 2 1 1 1 burst cycles to maximize system performance Delaying termination of the cycle can add wait states If internal termination is used dif...

Page 326: ...an 8 bit device with burst enabled The transfer results in a 4 beat burst and the data is driven on FB_D 31 24 NOTE The first beat of any write burst cycle has at least one wait state If the bus cycle...

Page 327: ...ure 18 28 shows a longword write through an 8 bit device with burst inhibited The transfer results in four individual transfers Figure 18 28 Longword Write Burst Inhibited to 8 Bit Port No Wait States...

Page 328: ...igure 18 29 Longword Read Burst from 8 Bit Port 3 2 2 2 One Wait State Figure 18 29 illustrates a write burst transfer with one wait state Figure 18 30 Longword Write Burst to 8 Bit Port 3 2 2 2 One W...

Page 329: ...32 shows a write cycle with one clock of address setup and address hold Figure 18 32 Longword Write Burst to 8 Bit Port 3 1 1 1 Address Setup and Hold 18 4 7 Misaligned Operands Because operands unlik...

Page 330: ...byte offset of 0x2 The next two bytes are transferred in this cycle In the third cycle byte 3 transfers The byte offset is now 0x0 the port supplies the final byte and the operation completes Example...

Page 331: ...well as the command set required for synchronous operations It also includes examples to better understand how to configure the DRAM controller for synchronous operations NOTE Unless otherwise noted...

Page 332: ...2 bit bus mode or 13 in 16 bit bus mode column address lines 2 bits of bank address and two pinned out chip selects The maximum row bits plus column bits equals 24 in 32 bit bus mode or 25 in 16 bit b...

Page 333: ...ight be configured as four 512K x 32 banks Banks are selected through the SD_BA 1 0 signals SDRAM RAMs that operate like asynchronous DRAMs but with a synchronous clock a pipelined multiple bank archi...

Page 334: ...nals are sent on the crossing of the positive edge of SD_CLK and the negative edge of SD_CLK Output data is referenced to the crossing of SD_CLK and SD_CLK both directions of crossing Timing Command s...

Page 335: ...address bits as needed The additional row or column address bits are programmed via the SDCR ADDR_MUX bits NOTE When the SDRAMC is configured to support an external 32 bit data bus It is not possible...

Page 336: ...tion Row bit x Col bit x Banks SDCR ADDR_ MUX Internal Address 27 26 25 24 23 12 11 10 9 2 64 Mbits 2M x 32 bit 11 x 8 x 4 00 1 2 RA11 0 BA1 0 CA7 0 4M x 16 bit 12 x 8 x 4 00 8M x 8 bit 12 x 9 x 4 00...

Page 337: ...2 CA11 CA9 CA8 13 x 11 x 4 01 CA11 CA9 CA8 RA12 14 x 10 x 4 10 CA9 CA8 RA13 RA12 1 Gbits 32M x 32 bit 12 x 11 x 4 00 CA11 CA9 CA8 RA11 0 BA1 0 CA7 0 13 x 10 x 4 01 CA9 CA8 RA12 14 x 9 x 4 10 CA8 RA13...

Page 338: ...Address 27 26 25 24 23 12 11 10 9 1 64 Mbits 4M x 16 bit 11 x 9 x 4 00 1 2 RA11 0 BA1 0 CA8 0 8M x 8 bit 12 x 9 x 4 00 16M x 4 bit 12 x 10 x 4 00 CA9 13 x 9 x 4 01 RA12 128 Mbits 8M x 16 bit 12 x 9 x...

Page 339: ...address width is 13 bits the column address can be 9 bits If all devices column address width is 9 bits the row address can be 11 bits The maximum row bits plus column bits equals 25 x16 data width me...

Page 340: ...the data valid window The SDRAMC also uses the SD_DQS 3 signals to determine when read data can be latched for SDR SDRAM however SDR memories do not provide DQS outputs Instead the SDRAMC provides a S...

Page 341: ...System SDRAM Controller 3 3V SDR SDRAM A 13 11 9 0 A10 AP BA 1 0 SD_A10 SD_A 23 0 SD_CKE SD_CLK SD_CS0 CS SD_RAS SD_SDR_DQS SDWE CLK CKE RAS SD_CAS CAS WE A 15 14 A 13 11 9 0 3 3V Flash A 21 0 D 31 0...

Page 342: ...out Considerations Due to the critical timing for DDR SDRAM a number of considerations should be taken into account during PCB layout Minimize overall trace lengths SDRAM Controller 2 5V DDR SDRAM A 1...

Page 343: ...ation should be between the processor and memory but closest to the processor The SD_CLK and SD_CLK signals can be terminated with a single termination resistor between the two clock phases A 100 120...

Page 344: ...chips These registers must be programmed during SDRAM initialization See Section 19 6 Initialization Application Information for more information on the initialization sequence Table 19 6 SDRAMC Memor...

Page 345: ...as the mode or extended mode register data 17 Reserved must be cleared 16 CMD Command This bit is write only and always returns a 0 when read 1 Generate an LMR LEMR command 0 Do not generate any comma...

Page 346: ...ted wiring is always recommended over unterminated 21 16 REF_CNT The average periodic interval at which the controller generates refresh commands to memory measured in increments of 64 SD_CLK period R...

Page 347: ...AM interface and is equal to the internal bus clock SD_CLK2 double frequency of SD_CLK DDR uses both edges of the bus frequency clock SD_CLK to read write data NOTE In all calculations for setting the...

Page 348: ...ions Note Count value is in SD_CLK periods for SDR and DDR mode 27 Reserved must be cleared 26 24 SWT2RWP Single write to read write precharge delay Limiting case is write to precharge SDR SWT2RWP tWR...

Page 349: ...fSD_CLK 1 Round up to nearest integer Example If tRP 20ns and fSD_CLK 99MHz Suggested value 20ns 99MHz 1 0 98 round to 1 Note Count value is in SD_CLK periods for SDR and DDR modes 11 8 REF2ACT Refres...

Page 350: ...ay to exit the error condition Table 19 10 SDCFG2 Field Descriptions Field Description 31 28 BRD2RP Burst read to read precharge delay Limiting case is read to read SDR BRD2RP BurstLength 1 DDR BRD2RP...

Page 351: ...SDRAM address space the memory controller generates the corresponding SDRAM command Table 19 12 lists SDRAM commands supported by the memory controller Table 19 11 SDCSn Field Descriptions Field Desc...

Page 352: ...bank of the new access If the address falls within the active row of an active bank it is a page hit and the read is issued as soon as possible pending any delays required by previous commands If the...

Page 353: ...ank for the new access followed by the WRITE command to the SDRAM The PALL PRE and ACTV commands if necessary can sometimes be issued in parallel with an on going data movement In SDR mode the memory...

Page 354: ...SDMR ADDR Do not overwrite the SDMR BA values This step can be performed in the same register write in step 2 4 Set the SDMR CMD bit 5 For DDR step 2 to 4 should be performed twice The first is for th...

Page 355: ...le state and waits for an ACTV command A3 BT Burst type 0 Sequential 1 Interleaved This setting should not be used because the SDRAMC does not support interleaved bursts A2 A0 BLEN Burst length Determ...

Page 356: ...self refresh mode before or after the memory controller clock is stopped restarted but not with the same control register write that clears CKE this would put the memory in power down mode To restart...

Page 357: ...bank of memory must be activated to allow read and write accesses The SDRAM controller supports paging mode to maximize the memory access throughout During operation the SDRAM controller maintains an...

Page 358: ...ry data beats The SDRAM controller manages the size translation packing unpacking between internal and external DRAM buses The burst size is the processor standard 16 bytes Four beats of 4 bytes on th...

Page 359: ...o negotiable host device on the USB bus The USB 2 0 OTG module interfaces to the processor s ColdFire core The USB controller is programmable to support host or device operations under firmware contro...

Page 360: ...ISCCR for more information The primary function of the transceiver is the physical signal conditioning of the external USB DP and DM cable signals for a USB 2 0 network Several USB system elements are...

Page 361: ...2 Mbps and low speed 1 5 Mbps transceiver 20 1 4 Modes of Operation The USB OTG module has two basic operating modes host and device Selection of operating mode is accomplished via the USBMODE CM bit...

Page 362: ...e OTG protocols The USB OTG module must be able to individually enable and disable the pull up and pull down resistors on DP and DM and it must be able to control and sense the levels on the USB VBUS...

Page 363: ...pter see Section 9 3 6 USB On the Go Controller Status Register UOCSR Table 20 3 Internal Control and Status Bits for USB OTG Module Signal Mnemonic Direction Comments Interrupt Trigger DP Pull down E...

Page 364: ...rs HWHOST N H D 32 R 0x1002_0001 20 3 1 3 20 9 0xFC0B_000C Device Hardware Parameters HWDEVICE N D 32 R 0x0000_0009 20 3 1 4 20 9 0xFC0B_0010 TX Buffer Hardware Parameters HWTXBUF N H D 32 R 0x8004_06...

Page 365: ...ntrol TXFILLTUNING N H 32 R W 0x0000_0000 20 3 4 11 20 28 0xFC0B_0180 Configure Flag Register CONFIGFLAG Y H D 32 R 0x0000_0001 20 3 4 12 20 30 0xFC0B_0184 Port Status Control PORTSC1 Y H D 32 R W 0xE...

Page 366: ...ly 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 REVISION 1 1 NID 0 0 ID W Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0...

Page 367: ...vant only for UTMI mode therefore it is relevant only to the USB OTG module in UTMI mode Always reads 00 00 8 bit data bus 60 MHz 3 Reserved always cleared 2 1 Reserved For the USB OTG module always 1...

Page 368: ...pable Always set Address 0xFC0B_0010 HWTXBUF Access User read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TXLC 0 0 0 0 0 0 0 TXCHANADD TXADD TXBURST W...

Page 369: ...e Buffer Hardware Parameters Register HWRXBUF Table 20 10 HWRXBUF Field Descriptions Field Description 31 16 Reserved 15 8 RXADD Receive address The number of address bits for the entire RX buffer Alw...

Page 370: ...ST Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 9 General Purpose Timer n Control Registers GPTIMERnCTL Table 20 12 GPTIMERnCTL Field Descriptions Field Description...

Page 371: ...o the register base address to find the beginning of the operational register space the location of the USBCMD register Address 0xFC0B_0100 HCIVERSION Access User read only 15 14 13 12 11 10 9 8 7 6 5...

Page 372: ...ion on embedded transaction translators 23 20 N_PTT Ports per transaction translator Non EHCI field Indicates number of ports assigned to each transaction translator within host controller 19 17 Reser...

Page 373: ...e the isochronous schedule relative to the current position of the executing host controller This field is always 0 0 The value of the least significant 3 bits indicates the number of microframes a ho...

Page 374: ...read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HC DC 0 0 DEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 375: ...icroframes Else Reserved 15 FS2 See the FS bit description below This is a non EHCI bit 14 ATDTW Add dTD TripWire This is a non EHCI bit This bit is used as a semaphore when a dTD is added to an activ...

Page 376: ...when the asynchronous schedule is inactive Doing so yields undefined results This bit used only in host mode Writing a 1 to this bit when the USB OTG module is in device mode has undefined results 5 A...

Page 377: ...sure the device is not in an attached state before initiating a device controller reset all primed endpoints must be flushed and the USBCMD RS bit must be cleared 0 RS Run Stop Host mode When set the...

Page 378: ...ete IOC bit set and the TD was from the asynchronous schedule This bit is also set by the host controller when a short packet is detected and the packet is on the asynchronous schedule A short packet...

Page 379: ...f 1 ms during the prelude to the connect and chirp 6 URI USB reset received A non EHCI bit When the controller detects a USB reset and enters the default state this bit is set Software can write a 1 t...

Page 380: ...EI USB error interrupt When completion of USB transaction results in error condition the controller sets this bit If the TD on which the error interrupt occurred also had its interrupt on complete IOC...

Page 381: ...rved must be cleared 16 NAKE NAK interrupt enable When this bit and the USBSTS NAKI bit are set an interrupt generates 0 Disabled 1 Enabled 15 9 Reserved must be cleared 8 SLE Sleep DC suspend enable...

Page 382: ...is cleared SOF for 1 ms frame If FRINDEX 13 3 equals the SOF value FRINDEX 2 0 is incremented SOF for 125 sec microframe 3 FRE Frame list rollover enable When this bit and the USBSTS FRI bit are set...

Page 383: ...INDEX Field Descriptions Field Description 31 14 Reserved must be cleared 13 0 FRINDEX Frame index The value in this register increments at the end of each time frame microframe Bits N 3 are for the f...

Page 384: ...ister In host mode it is the ASYNCLISTADDR register in device mode it is the EPLISTADDR register See Section 20 3 4 8 Endpoint List Address Register EPLISTADDR for more information Table 20 24 PERIODI...

Page 385: ...iptions Field Description 31 5 ASYBASE Link pointer low LPL These bits correspond to memory address signal 31 5 This field may only reference a queue head QH Used only in host mode 4 0 Reserved must b...

Page 386: ...iption 31 Reserved must be cleared 30 24 TTHA TT Hub Address This field is used to match against the Hub Address field in a QH or siTD to determine if the packet is routed to the internal TT for direc...

Page 387: ...ribed below can minimize back offs Address 0xFC0B_0164 TXFILLTUNING Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 T...

Page 388: ...second in a highly utilized bus Choosing a value too high for this register is not desired as it can needlessly reduce USB utilization The time unit represented in this register is 1 267 s when a dev...

Page 389: ...R OCC OCA PEC PE CSC CCS W w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Figure 20 28 Port Status and Control Register PORTSC1 Table 20 32 PORTSC1 Field Descriptions Field Description 31 30 PTS Po...

Page 390: ...wake up events This field is 0 if the PP bit is cleared or the module is in device mode In host mode this can work with an external power control circuit 19 16 PTC Port test control Any value other t...

Page 391: ...river Device mode This bit is a read only status bit Device reset from the USB bus is also indicated in the USBSTS register 0 Port is not in reset 1 Port is in reset 7 SUSP Suspend 0 Port not in suspe...

Page 392: ...the OCA bit Software clears this bit by writing a 1 For host mode the user can provide over current detection to the USBn_PWRFAULT signal for this condition For device only implementations this bit mu...

Page 393: ...on hub hardware is setting an already set bit i e the bit remains set Software clears this bit by writing a 1 to it This field is cleared if the PP bit is cleared 0 No change 1 Connect status has chan...

Page 394: ...lear this bit 21 1MSS 1 millisecond timer interrupt status This bit is set once every millisecond Software must write a 1 to clear this bit 20 BSEIS B session end interrupt status Indicates when VBUS...

Page 395: ...valid threshold 9 AVV A VBus valid 0 VBus is below A VBus valid threshold 1 VBus is above A VBus valid threshold 8 ID USB ID 0 A device 1 B device 7 6 Reserved must be cleared 5 IDPU ID Pull up Provi...

Page 396: ...FIFO becomes significant when stream disable is active See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature Also in systems with high system bus utilizatio...

Page 397: ...s register 00 Idle default for the USB OTG module 01 Reserved 10 Device controller 11 Host controller Note The USB OTG module must be initialized to the desired operating mode after reset Address 0xFC...

Page 398: ...st write a 1 to the corresponding bit when posting a new transfer descriptor to an endpoint Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and...

Page 399: ...15 4 Reserved must be cleared 3 0 ERBR Endpoint receive buffer ready One bit for each endpoint indicates status of the respective endpoint buffer The hardware sets this bit in response to receiving a...

Page 400: ...0 0 0 0 0 TXE 0 0 0 TXT 0 TXS 0 0 0 0 0 0 0 0 RXE 0 0 0 RXT 0 RXS W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Figure 20 36 Endpoint Control 0 EPCR0 Table 20 40 EPCR0 Field...

Page 401: ...I 0 TXT TXD TXS W TXR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 RXE 0 RXI 0 RXT RXD RXS W RXR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 37 End...

Page 402: ...ware must write a 1 to this bit to synchronize the data PIDs between the host and device This bit is self clearing 5 RXI RX data toggle inhibit This bit is only for testing and should always be writte...

Page 403: ...packets to FS and LS speed devices In device mode data structures are similar to those in the EHCI specification and used to allow device responses to be queued for each of the active pipes in the dev...

Page 404: ...tion requires this internal resistor to be disabled via the CCM and 15k external resistors to connect from DP and DM signals to ground 20 5 Initialization Application Information 20 5 1 Host Operation...

Page 405: ...tem software must write the ASYNCLISTADDR register with the address of a control or bulk queue head Software must then enable the asynchronous schedule by setting the asynchronous schedule enable ASE...

Page 406: ...ointer longword and continues through the end of the buffer pointers longwords After a transfer is complete the dTD status longword updates in the dTD pointed to by the currentTD pointer While a packe...

Page 407: ...ytes IOC 0 0 0 MultO 0 0 Status 0x0C1 Buffer Pointer Page 0 Current Offset 0x101 Buffer Pointer Page 1 Reserved 0x141 Buffer Pointer Page 2 Reserved 0x181 Buffer Pointer Page 3 Reserved 0x1C1 Buffer P...

Page 408: ...ro length packet from the host to retire the current dTD Setting this bit disables the zero length packet When the device is transmitting the hardware does not append any zero length packet When recei...

Page 409: ...5 3 6 Managing Transfers with Transfer Descriptors 20 5 2 2 1 Next dTD Pointer Offset 0x0 The next dTD pointer is used to point the device controller to the next dTD in the linked list Table 20 45 Mu...

Page 410: ...e successful completion of the transaction The maximum value software may store in the field is 5 4K 0x5000 This is the maximum number of bytes 5 page pointers can access Although possible to create a...

Page 411: ...e status of the last transaction performed on this dTD The bit encodings are Bit Status Field Description 7 Active Set by software to enable the execution of transactions by the device controller 6 Ha...

Page 412: ...he USBINTR to enable the desired interrupts For device operation setting UE UEE PCE URE and SLE is recommended For a list of available interrupts refer to Section 20 3 4 3 USB Interrupt Enable Registe...

Page 413: ...rsal Serial Bus Specification Revision 2 0 Figure 20 41 depicts the state of a USB 2 0 device Figure 20 41 USB 2 0 Device States States powered attach defaultFS HS suspendFS HS are implemented in the...

Page 414: ...1 Clear all setup token semaphores by reading the EPSETUPSR register and writing the same value back to the EPSETUPSR register 2 Clear all the endpoint complete status bits by reading the EPCOMPLETE...

Page 415: ...ective suspend by using electrical signaling to indicate remote wake up The ability of a device to signal remote wake up is optional The USB OTG is capable of remote wake up signaling When the USB OTG...

Page 416: ...erve the total number of endpoints required for device operation The only exception is that control endpoints must use both directions on a single endpoint number to function as a control endpoint End...

Page 417: ...its A single write to the EPCRn register can ensure both stall bits are set at the same instant NOTE Any write to the EPCRn register during operational mode must preserve the endpoint type field perfo...

Page 418: ...is considered For example if endpoint 3 transmit direction is configured as a bulk pipe expect the host to send IN requests to that endpoint This USB OTG module prepares packets for each endpoint dir...

Page 419: ...y commences A dTD is retired by the device controller when the packets described in the transfer descriptor are completed Each dTD describes N packets to transfer according to the USB variable length...

Page 420: ...ket termination allows transfers larger than the total bytes field spanning across two or more dTDs Upon successful completion of the packet s described by the dTD the active bit in the dTD is cleared...

Page 421: ...local software byte array copy and execute status handshake phases NOTE After receiving a new setup packet status and or handshake phases may remain pending from a previous control sequence These shou...

Page 422: ...packets on a control endpoint according to the device controller state 20 5 3 4 5 Isochronous Endpoint Operation Isochronous endpoints used for real time scheduled delivery of data and their operatio...

Page 423: ...nsfer Internal to the design the device controller hardware masks that prime start until the next frame boundary This behavior is hidden from the DCD but occurs so the device controller can match the...

Page 424: ...out ahead of the device controller by at least two micro frames Isochronous Pipe Synchronization When it is necessary to synchronize an isochronous data pipe to the host the micro frame number FRINDEX...

Page 425: ...ue head after the dTD is retired see Section 20 5 3 6 1 Software Link Pointers Figure 20 42 Endpoint Queue Head Diagram In addition to current and next pointers and the dTD overlay examined in Section...

Page 426: ...sfers require special treatment by the DCD A setup transfer does not use a dTD but instead stores the incoming data from a setup packet in an 8 byte buffer within the dQH Upon receiving notification o...

Page 427: ...are Link Pointers NOTE Check the status of each dTD to determine completed status 20 5 3 6 2 Building a Transfer Descriptor Before a transfer can be executed from the linked list a dTD must be built t...

Page 428: ...t If clear go to 3 If set continue to 6 6 Clear the USBCMD ATDTW bit 7 If status bit read in step 4 is 1 DONE 8 If status bit read in step 4 is 0 then go to case 1 step 1 20 5 3 6 4 Transfer Completio...

Page 429: ...ime depending on the USB bus activity It is not desirable to have this wait loop within an interrupt service routine 3 Read the EPSR register to ensure that for all endpoints commanded to be flushed t...

Page 430: ...lete the number of packets defined in the dQH mult field within the given micro frame For scheduled data delivery DCD may need to readjust the data queue because a fulfillment error causes the device...

Page 431: ...e EHCI specification Device and OTG operation are not specified in the EHCI specification and thus the implementation supported in the USB OTG module is proprietary 20 5 5 1 Embedded Transaction Trans...

Page 432: ...ansactions through the root hub It is demonstrated here how hub address and endpoint speed fields should be set for directly attached FS LS devices and hubs 1 QH for direct attach FS LS asynchronous b...

Page 433: ...following sections assume the reader is familiar with the EHCI and USB 2 0 transaction translator operational models Microframe Pipeline The EHCI operational model uses the concept of H frames and B f...

Page 434: ...ator ensures no full low speed packet babbles into SOF time USB 2 0 11 17 4 Transaction tracking for 2 data pipes USB 2 0 11 17 5 Clear_TT_Buffer capability provided though the use of the TTCTRL regis...

Page 435: ...e fields in the USB OTG module in the operation registers should always be written to zero This is an EHCI requirement of the device controller driver that must be adhered to Read operations by the mo...

Page 436: ...PR bit to reset the device Software shall clear the PORTSCn PR bit after 10 ms This step necessary in a standard EHCI design may be omitted with this implementation Should the EHCI host controller dri...

Page 437: ...1 Block Diagram The LCD controller block diagram is shown below Figure 21 1 LCDC Block Diagram 21 1 2 Features The LCDC provides the following features Support for single non split screen monochrome...

Page 438: ...4 8 bit for monochrome panels Panel interface of 12 16 18 bit for color panels For 4 bpp and 8 bpp a palette table is used for re mapping of data from memory independent of type of panel used For the...

Page 439: ...atrix Horizontal sync pulse Indicates start of next line LCD_LSCLK O Shift clock Clock for latching data into the display driver s internal shift register LCD_ACD LCD_OE O Passive matrix Alternate cry...

Page 440: ...ontrol Register LCD_RMCR 32 R W 0x0000_0000 21 3 14 21 17 0xFC0A_C038 LCD Interrupt Configuration Register LCD_ICR 32 R W 0x0000_0000 21 3 15 21 18 0xFC0A_C03C LCD Interrupt Enable Register LCD_IER 32...

Page 441: ...s image 1 0 Reserved must be cleared Address 0xFC0A_C004 LCD_SR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 XMAX 0 0 0 0...

Page 442: ...Figure 21 4 LCD Virtual Page Width Register LCD_VPW Table 21 6 LCD_VPW Field Descriptions Field Description 31 10 Reserved must be cleared 9 0 VPW Virtual page width Defines the virtual page width of...

Page 443: ...position in pixel count from 0 to LCD_SR XMAX 15 10 Reserved must be cleared 9 0 CYP Cursor Y position Indicates the cursor s vertical starting position in pixel count from 0 to LCD_SR YMAX Address 0...

Page 444: ...rsor 23 21 Reserved must be cleared 20 16 CH Cursor height Specifies the height of the hardware cursor in pixels This field can be any value between 1 and 31 Setting this field to zero disables the cu...

Page 445: ...sor blue field Defines the blue component of the cursor color in color mode 0x00 No blue 0x3F Full blue Address 0xFC0A_C018 LCD_PCR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 446: ...ield description for TFT COLOR setting usage 0 The LCD panel is a monochrome display 1 The LCD panel is a color display 29 28 PBSIZ Panel bus width Specifies the panel bus width Applicable for monochr...

Page 447: ...ormal direction 1 Vertical scan in reverse direction 15 ACDSEL LCD_ACD clock source select Selects the clock source used by the alternative crystal direction counter 0 Use LCD_FLM as clock source for...

Page 448: ...e LCD_LSCLK periods 25 16 Reserved must be cleared 15 8 H_WAIT_1 Wait between LCD_OE and LCD_HSYNC In TFT mode this field specifies the number of LCD_LSCLK periods between the end of LCD_OE signal and...

Page 449: ...ulse and the beginning of the LCD_VSYNC pulse for active mode TFT 1 This field has no meaning in passive non color mode The actual delay is V_WAIT_1 lines In passive color mode this field is the delay...

Page 450: ...nce at the beginning of each frame For example in 4 bpp mode setting POS 16 shifts the data 16bits which equates to panning the image by 4 pixels to the left Note Use the LSSAR register to shift the d...

Page 451: ...one of the two grayscale shading densities This field is programmable to any value between 0 and 16 0 and 16 are already defined as two of the four colors 3 0 GRAY1 Grayscale 1 Represents one of the...

Page 452: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 14 LCD PWM Contrast Control Register LCD_PCCR Table 21 15 LCD_PCCR Field Descriptions Field Description 31 25 Reserved must be cleared 24 16 CLS_HI_ WIDTH LC...

Page 453: ...0 Burst length is dynamic 1 Burst length is fixed 30 21 Reserved must be cleared 20 16 HM DMA high mark Establishes the high mark for DMA requests For dynamic burst length after the DMA request is mad...

Page 454: ...ield Description 31 1 Reserved must be cleared 0 SELF_REF Self refresh mode enable 0 Disable self refresh 1 Enable self refresh Address 0xFC0A_C038 LCD_ICR Access User read write 31 30 29 28 27 26 25...

Page 455: ...1 Reserved must be cleared 0 INT_CON Interrupt condition Determines if an interrupt condition is set at the beginning or the end of frame condition Refer to table in the INT_SYN field description for...

Page 456: ...iptions Field Description 31 8 Reserved must be cleared 7 GWUDR Graphic window underrun error interrupt enable 0 Mask interrupt 1 Enable interrupt 6 GWERR Graphic window error response interrupt enabl...

Page 457: ...eived a bus error It is cleared by reading the status register at power on reset or when the LCDC is disabled 0 Interrupt has not occurred 1 Interrupt has occurred 5 GWEOF Graphic window end of frame...

Page 458: ...has occurred Address 0xFC0A_C050 LCD_GWSAR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R GWSA 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 459: ...or a total of GW_YMAX lines The graphic window size cannot be set to 0 Note The maximum supported panel size is 800x600 pixels Therefore the maximum value for this bit field is 0x258 Address 0xFC0A_C0...

Page 460: ...6 shifts 16 bits which means panning the image by 4 pixels left Note Use the LGWSAR register to shift the data more than 32 bits or for 18 bpp panning To achieve panning of the final image by N bits A...

Page 461: ...LCD screen 1 Graphic window totally opaque completely visible on the LCD screen 23 GWCKE Graphic window color keying enable Enable or disable graphic window color keying 0 Disable color keying of grap...

Page 462: ...and write data use the least significant 12 or 18 bits NOTE Byte or word access to the RAM corrupts its contents Address 0xFC0A_C068 LCD_GWDCR Access User read write 31 30 29 28 27 26 25 24 23 22 21 2...

Page 463: ...code represents a 12 bit color Because only four bits are used to encode the color a maximum of 16 colors can be selected out of a palette of 4096 The first 16 mapping RAM entries must be written to...

Page 464: ...epresents an 18 bit color Because eight bits are used to encode the color a maximum of 256 colors can be selected out of a palette of 256K All 256 mapping RAM entries must be written to define the cod...

Page 465: ...ing address register LCD_SSAR represented by the shaded area in Figure 21 27 for display on the LCD panel The maximum page width is specified by the virtual page width VPW parameter Virtual page heigh...

Page 466: ...raphic hardware cursor functions Similar to the screen the virtual page width graphic window start address and graphic window width and height are software programmable The position of the graphic win...

Page 467: ...e effect until the beginning of the next frame A typical panning algorithm includes an interrupt at the beginning of the frame In the interrupt service routine POS and or SSA are updated the old value...

Page 468: ...it 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 P6 P7 8 bpp Mode Byte Address Sample Bit to Pixel Mapping 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P0 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit...

Page 469: ...voltages vary the visual gray effect may or may not be linearly related to the frame rate A logarithmic scale such as 0 1 4 1 2 and 1 might be more pleasing than a linearly spaced scale such as 0 5 16...

Page 470: ...it RGB code from the mapping RAM is output to the FRC blocks that independently process the code corresponding to the red green and blue components of each pixel to generate the required shade and int...

Page 471: ...eescale Semiconductor 21 35 Figure 21 33 Passive Matrix Color Pixel Generation 1 0 1 1 0 0 7 6 5 4 3 2 1 0 4 bpp Data 8 bpp Data 1 0 1 1 1 1 1 0 1 1 Color RAM Inside LCDC 256 rows R G B FRC FRC FRC 0...

Page 472: ...zeroes and ones that appear over the frames The LCDC can generate 16 simultaneous gray scale levels Table 21 33 Gray Palette Density Gray Code Hexadecimal Density Density Decimal 0 0 0 1 1 8 0 125 2 1...

Page 473: ...re multiplexed with other functions on the device and must be configured for LCDC operation before they can be used 21 4 9 2 Passive Matrix Panel Interface Signals Figure 21 36 shows the LCD interface...

Page 474: ...toggles after a pre programmed number of LCD_FLM pulses This signal refreshes the LCD panel NOTE The LCD_D bus width is programmable to 1 2 4 or 8 bits in monochrome mode the COLOR bit in the panel co...

Page 475: ...ntal sync pulse width defines the width of the LCD_FLM pulse and H_WIDTH must be at least 1 H_WAIT_2 defines the delay from the end of LCD_LP to the beginning of data output NOTE All parameters are de...

Page 476: ...clock LCD_LSCLK horizontal sync pulse LCD_HSYNC the LCD_LP pin in passive mode vertical sync pulse LCD_VSYNC the LCD_FLM pin in passive mode output enable LCD_OE the LCD_ACD pin in passive mode and l...

Page 477: ...CD_D 5 0 bits define blue In 12 bit mode the LCD_D 17 14 bits define red the LCD_D 11 8 bits define green and the LCD_D 5 2 bits define blue In 16 bit mode the LCD_D 17 13 bits define red the LCD_D 11...

Page 478: ...0 G4 0 1 G4 0 2 LCD_LSCLK 1 2 3 m m 1 239 240 LCD_HSYNC LCD_VSYNC LCD_HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n LINE 1 LCD_D8 G3 0 0 G3 0 1 G3 0 2 LCD_D7 G2 0 0 G2 0 1 G2 0 2 LCD_D6 G1 0 0 G1 0 1 G1 0...

Page 479: ...elay of one LCD_HSYNC time one line period before LCD_VSYNC The LCD_HSYNC pulse is output during the V_WAIT_1 delay For V_WIDTH vertical sync pulse width 0 LCD_VSYNC encloses one LCD_HSYNC pulse For V...

Page 480: ...Liquid Crystal Display Controller LCDC MCF52277 Reference Manual Rev 1 21 44 Freescale Semiconductor...

Page 481: ...FO memory and bus interface The ADC block includes the bias network and touchscreen pen state detection ADC control works together with the ADC to implement the ADC function Clock generator generates...

Page 482: ...ned 12 bit binary output with 2 LSB INL 1 LSB DNL 2 LSB offset error and 4 LSB gain error Ratiometric measurements drivers support differential mode Up to eight auxiliary input channels are available...

Page 483: ...Address Register Width bits Access Reset Value Section Page 0xFC0A_8000 ASP Control Register ASP_CR 32 R W 0x0008_0000 22 3 1 22 4 0xFC0A_8004 ASP Sampling Setting Register ASP_SET 32 R W 0x7787_0000...

Page 484: ...according to other fields in ASP_CR ASPE s effect on ASP operation depends on the timing before an ADC_CLK rising edge and the current state of the ASP state machine The ASP state machine operates on...

Page 485: ...asurement sequences when TSE and AUTO are set It also automatically clears the ASPE bit 0 Pen detection phase disabled 1 Pen detection phase enabled 19 MDIS Module Disable Forces the ADC into a power...

Page 486: ...e ADC samples only the touchscreen inputs the general purpose inputs or both sets of inputs in a single single round or auto continuous way 7 0 APTN ASP sampling pattern If the corresponding ADC chann...

Page 487: ...ample Setting Register ASP_SET Table 22 4 ASP_SET Field Descriptions Field Description 31 Reserved must be cleared 30 28 REFP Positive reference Selects the positive reference input to the ADC when fu...

Page 488: ...al operation ASP_CR MODE 00 0 Bias transistor off 1 Bias transistor on Address 0xFC0A_8008 ASP_TIM Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 489: ...V IE 0 PU IE PD IE PFL DE PFL IE PFF IE PDR IE W Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 5 ASP Interrupt Control Register ASP_ICR Table 22 6 ASP_ICR Field Descr...

Page 490: ...s and disables the pen data ready interrupt request 1 Enable the pen sample data ready interrupt 0 Disable the pen sample data ready interrupt Address 0xFC0A_8010 ASP_ISR Access User read write 31 30...

Page 491: ...the level programmed in FIFO_WM 1 PFFF Pen FIFO full flag Indicates the sample FIFO is full Reading data out of the FIFO so the FIFO is not full clears PFFF automatically 0 Pen FIFO is not full 1 Pen...

Page 492: ...ccess User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 FFRP 0 0 0 0 0 0 0 0 0 0 FFWP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 493: ...Field Description 31 7 Reserved must be cleared 6 0 CLKD ASP clock divider The ASP clock is derived using the following formulas If 15 CLKD 127 Eqn 22 3 If 1 CLKD 14 and CLKD is even Eqn 22 4 If 1 CLK...

Page 494: ...TO AZE ASPE MCU Direct Sample Mode 00 X X 0 No data is written to the FIFO The ASP_SET register determines the configuration of the bias switches and reference input muxes However there is no conversi...

Page 495: ...is set the ADC starts the conversion of the AZX X AZY and Y coordinates sets The result is written to pen sample FIFO Between the conversion of AZX to X and AZY to Y no measurement idle time is insert...

Page 496: ...of each round of conversion there is an option to insert round idle time using ASP_TIM RIDLECNT Between each round of conversion you may insert one pen down detection phase after the round idle phase...

Page 497: ...UTO AZE PENE MIDLECNT and RIDLECNT are not relevant to the operation Table 22 12 General ADC Operating Modes TSE 0 ASP_CR Field Pen Sample FIFO Data Format Notes AUTO ASPE 0 0 No data is written to th...

Page 498: ...pare for the next operation l MCU reads out the Y measurement result and data ready interrupt is cleared automatically Figure 22 11 Manual Mode For General Purpose ADC Application a MCU sets ASP_SET t...

Page 499: ...ation is complete the ASP parks on the pen detect state b Pen down event is detected and the pen down interrupt occurs c MCU responds to the interrupt and clears masks the interrupt d MCU sets ASPE to...

Page 500: ...22 13 Mode 01 Auto Part 1 Figure 22 14 Mode 01 Auto Part 2 a When ASP configuration is complete the ASP parks on pen detection state b Pen down event is detected and the pen down interrupt occurs c M...

Page 501: ...oftware must stop the conversion according to the measurement results 22 5 4 Touchscreen Mode 10 Single Round Touchscreen mode 10 single round is used for touchscreen controlled auxiliary channel meas...

Page 502: ...U depending on the PENE setting The ASP is ready to detect the next pen down event i MCU clears the pen up interrupt NOTE If MIDLECNT is equal to zero remove the IDLE measurement phase 22 5 5 Touchscr...

Page 503: ...l MCU uploads the conversion results which clears the FIFO watermark interrupt m Pen up event is detected and the pen up interrupt occurs n ASPE is cleared automatically after detection of pen up inte...

Page 504: ...rsion results here g Pen up event is detected and the pen up interrupt occurs If FIFO watermark interrupt is not used the conversion results may be uploaded here h ASPE is cleared automatically or by...

Page 505: ...st round of measurement k FIFO watermark interrupt occurs l MCU uploads the conversion results which clears the FIFO watermark interrupt m Pen up event is detected and the pen up interrupt occurs n AS...

Page 506: ...he conversions c ASP begins a round of conversions d ASP completes the round of conversions and enters idle state again e If the FIFO watermark level is set to the number of active auxiliary channels...

Page 507: ...conversion k MCU uploads the last round of conversion results which clears the FIFO watermark interrupt NOTE If MIDLECNT is equal to zero remove the IDLE measurement phase If RIDLECNT is equal to zero...

Page 508: ...asurement phase 22 5 11 Touchscreen Calibration Auto Touchscreen calibration auto is similar to the single round in capturing the calibration data set However it improves the calibration precision by...

Page 509: ...ion d ASP clears the FIFO watermark interrupt by uploading the data from the FIFO e Steps c and d repeat f The FIFO watermark interrupt for the last round of calibration occurs g ASP clears ASPE to st...

Page 510: ...Touchscreen Controller Analog to Digital Converter MCF52277 Reference Manual Rev 1 22 30 Freescale Semiconductor...

Page 511: ...ot only designed to be used as a vehicle serial data bus meeting the specific requirements of this field real time processing reliable operation in the EMI environment of a vehicle cost effectiveness...

Page 512: ...transceiver The transceiver provides the transmit drive waveshaping and receive compare functions required for communicating on the CAN bus It can also provide protection against damage to the FlexCAN...

Page 513: ...th each configurable as Rx or Tx all supporting standard and extended messages Listen only mode capability Individual mask registers for each message buffer Reception queue support Programmable transm...

Page 514: ...s and the NOTRDY and FRZACK bits in CANMCR are set The CPU is allowed to read and write the error counter registers in other modes they are read only After engaging one of the mechanisms to place the...

Page 515: ...frozen and the module operates in a CAN error passive mode Only messages acknowledged by another CAN station are received If FlexCAN detects a message that has not been acknowledged it flags a BIT0 er...

Page 516: ...should only be changed while the module is in freeze mode Supervisor User Access Registers 0xFC02_0004 FlexCAN Control Register CANCTRL 32 Y N R W 0x0000_0000 23 3 2 23 9 0xFC02_0008 Free Running Time...

Page 517: ...enter freeze mode when the BKPT line is asserted or the HALT bit is set Clearing this bit causes the FlexCAN to exit freeze mode Refer to Section 23 1 3 2 Freeze Mode for more information 0 FlexCAN i...

Page 518: ...ess controlled by the SUPV bit are restricted to supervisor mode 22 21 Reserved must be cleared 20 LPMACK Low power mode acknowledge Indicates that FlexCAN is disabled Disabled mode cannot be entered...

Page 519: ...factor Defines the ratio between the clock source frequency set by CLK_SRC bit and the serial clock S clock frequency The S clock period defines the time quantum of the CAN protocol For the reset val...

Page 520: ...d 6 BOFFREC Bus off recovery mode Defines how FlexCAN recovers from bus off state If this bit is cleared automatic recovering from bus off state occurs according to the CAN Specification 2 0B If the b...

Page 521: ...LOM Listen only mode Configures FlexCAN to operate in listen only mode In this mode transmission is disabled all error counters are frozen and the module operates in a CAN error passive mode Only mess...

Page 522: ...ched a message buffer MB through a mask may be transferred into the MB upon release but may no longer match Table 23 5 Mask Examples for Normal Extended Messages Base ID ID28 ID18 IDE Extended ID ID17...

Page 523: ...rules for FlexCAN bus state transitions If the value of TXECTR or RXECTR increases to be greater than or equal to 128 the FLTCONF field in the error and status register ERRSTAT is updated to reflect e...

Page 524: ...27 it is not incremented further even if more errors are detected while being a receiver At the next successful message reception the counter is set to a value between 119 and 127 to resume to error a...

Page 525: ...sive 13 ACKERR Acknowledge error Indicates whether an acknowledgment has been correctly received for a transmitted message 0 No ACK error was detected since the last read of this register 1 An ACK err...

Page 526: ...exCAN state changes to bus off If the CANCTRL BOFFMSK bit is set an interrupt request is generated This interrupt is not requested after reset 1 ERRINT Error interrupt Indicates that at least one of t...

Page 527: ...nfigures the message buffer an identifier field for frame identification and up to 8 bytes of data Address 0xFC02_0030 IFLAG Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1...

Page 528: ...identifier 11 bits and the extended identifier 18 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0 CODE SRR IDE RTR LENGTH TIME STAMP 0x4 Standard ID 28...

Page 529: ...d as a successful bit transmission 0 Indicates the current MB has a data frame to be transmitted 1 Indicates the current MB has a remote frame to be transmitted 19 16 LENGTH Length of data in bytes In...

Page 530: ...ull buffer 0010 If the code indicates OVERRUN but the CPU reads the C S word and then unlocks the MB when a new frame is written to the MB the code returns to FULL 0110 If the code already indicates O...

Page 531: ...quest frame with the same ID is received This message buffer participates simultaneously in the matching and arbitration processes The matching process compares the ID of the incoming remote request f...

Page 532: ...le 23 12 Similarly a Tx MB with a 1000 code is inactive refer to Table 23 13 An MB not programmed with 0000 or 1000 is temporarily deactivated does not participate in the current arbitration matching...

Page 533: ...was no MB to transmit but the CPU wrote to the C S word of any MB after the previous arbitration finished When MBM is in idle or bus off state and the CPU writes to the C S word of any MB Upon leaving...

Page 534: ...cause after a frame was received and the CPU services the MB by reading the C S word followed by unlocking the MB the CODE field does not return to EMPTY It remains FULL as explained in Table 23 12 If...

Page 535: ...w more time to the CPU for servicing the MBs By programming more than one MB with the same ID received messages are queued into the MBs The CPU can examine the time stamp field of the MBs to determine...

Page 536: ...d after they are scanned no re evaluation is done to determine a new match winner If an Rx MB with a matching ID is deactivated during the matching process after it was scanned then this MB is marked...

Page 537: ...empty then reading the control and status word does not lock the MB NOTE Deactivation takes precedence over locking If the CPU deactivates a locked Rx MB then its lock status is negated and the MB is...

Page 538: ...ter the transmission has completed successfully The free running timer can optionally be reset upon the reception of a frame into message buffer 0 This feature allows network time synchronization to b...

Page 539: ...Segments within the Bit Time Table 23 16 gives an overview of the CAN compliant segment settings and the related parameter values 1 For further explanation of the underlying concepts please refer to I...

Page 540: ...k domains Therefore it may take some time to fully propagate its effects The CANMCR SOFT_RST bit remains asserted while soft reset is pending so software can poll this bit to know when the reset has c...

Page 541: ...e initialized as required 4 Initialize the RX individual mask registers for acceptance mask as needed 5 Initialize FlexCAN interrupt handler a Initialize the interrupt controller registers for any nee...

Page 542: ...FlexCAN MCF52277 Reference Manual Rev 1 23 32 Freescale Semiconductor...

Page 543: ...ies of pulses having programmable period and duty cycle With a suitable low pass filter the PWM can be used as a digital to analog converter Figure 24 1 PWM Block Diagram Internal Bus Clock fsys 2 Clo...

Page 544: ...modules each with its own control and counter registers although only four channels have an output signal The memory map for the PWM is shown below NOTE Longword accesses to any of the PWM registers...

Page 545: ...MCM ISR Address 0xFC09_0020 PWME Access User Read Write 7 6 5 4 3 2 1 0 R PWME7 0 PWME5 0 PWME3 0 PWME1 0 W Reset 0 0 0 0 0 0 0 0 Figure 24 2 PWM Enable Register PWME Table 24 2 PWME Field Description...

Page 546: ...ansition 1 PWME1 PWM Channel 1 Output Enable If enabled the PWM signal becomes available at PWMOUT1 when its corresponding clock source begins its next cycle 0 PWM output disabled 1 PWM output enabled...

Page 547: ...information on how the different clock rates are generated The even numbered channels clock select has no effect when the corresponding PWMCTL CONn n 1 bit is set For example if PWMCTL CON01 equals 1...

Page 548: ...tion of the concatenation function 3 Reserved must be cleared 2 0 PCKA Clock A prescaler select These three bits control the rate of Clock A which can be used for PWM channels 1 and 5 Address 0xFC09_0...

Page 549: ...WM signal and PWMOUT4 is disabled The channel 5 clock select polarity center align enable and enable bits control this concatenated output 5 CON23 Concatenates PWM channels 2 and 3 to form one 16 bit...

Page 550: ...the scale counter to load the new scale value PWMSCLB Address 0xFC09_0028 PWMSCLA Access User Read Write 7 6 5 4 3 2 1 0 R SCALEA W Reset 0 0 0 0 0 0 0 0 Figure 24 8 PWM Scale A Register PWMSCLA Table...

Page 551: ...e the immediate load of duty and period registers with values from the buffers and the output to change according to the polarity bit The counter is also cleared at the end of the effective period see...

Page 552: ...To calculate the output duty cycle high time as a percentage of period for a particular channel Eqn 24 4 Table 24 10 PWMCNTn Field Descriptions Field Description 7 0 COUNT Current value of the PWM up...

Page 553: ...9_0041 PWMDTY5 0xFC09_0042 PWMDTY6 0xFC09_0043 PWMDTY7 Access User Read Write 7 6 5 4 3 2 1 0 R DUTY W Reset 1 1 1 1 1 1 1 1 Figure 24 12 PWM Duty Registers PWMDTYn Table 24 12 PWMDTYn Field Descripti...

Page 554: ...PWM7IN input 1 Change in PWM7IN input 6 IE PWM interrupt enable An interrupt is triggered to the device s interrupt controller when PWMSDN IF is set 0 Interrupt is disabled 1 Interrupt is enabled 5 R...

Page 555: ...so disabled when all PWM channels are disabled PWMEn 0 Clock A and B are scaled values of the input clock The value is software selectable for clock A and B and has options of 1 1 2 or 1 128 times the...

Page 556: ...re loaded Otherwise when changing rates the counter would have to count down to 0x01 before counting at the proper rate Forcing the associated counter to re load the scale register value every time P...

Page 557: ...ts in the PWMPOL register is set the associated PWM channel output is high at the beginning of the waveform then goes low when the duty count is reached Conversely if the polarity bit is zero the outp...

Page 558: ...immediate load of duty and period registers with values from the buffers and the output to change according to the polarity bit When the channel is disabled PWMEn 0 the counter stops When a channel b...

Page 559: ...counts from 0 to the value in the period register minus 1 NOTE Changing the PWM output mode from left aligned to center aligned output or vice versa while channels are operating can cause irregularit...

Page 560: ...e When the PWM counter decrements and reaches zero the counter direction changes from a down count back to an up count and a load from the double buffer period and duty registers to the associated reg...

Page 561: ...gure 24 20 when channels 2 and 3 are concatenated channel 2 registers become the high order bytes of the double byte channel When channels 0 and 1 are concatenated channel 0 registers become the high...

Page 562: ...mmarizes the boundary conditions for the PWM regardless of the output mode left or center aligned and 8 bit normal or 16 bit concatenation Table 24 15 16 bit Concatenation Mode Summary CONnn PWMEn PPO...

Page 563: ...hers EDS Converted block guide Formatted registers bit descriptions Only 4 PWM channels for Tosca 6 in block guide No emergency shutdown for Tosca 14 Apr 2004 E Southers EDS Removed redundant text in...

Page 564: ...ections 14 Jul 2004 E Southers EDS Fixed addresses for PWM Duty Registers in Figure 24 12 20 Sept 2004 E Southers EDS Tosca Rev 1 22 Oct 2004 E Southers EDS Converted to SRS3 2 template Added PWM 4 PW...

Page 565: ...d Kirin0u conditional tag and assigned it to entries tagged for Kirin0 1 1 12 Jan 2007 E Southers EDS Initial version loaded into DesignSync N A 1 2 19 Jan 2007 M Tsurikov MST In the memory map condit...

Page 566: ...paration for Kirin0 Rev 1 1 18 11 Jun 2007 M Tsurikov MST Preparation for Kirin0u Rev 1 1 19 1 20 14 Aug 2007 M Tsurikov MST Preparation for Kirin2e Rev 5 1 21 15 Aug 2007 E Southers EDS Preparation f...

Page 567: ...PWME PWME7 1 31 1 32 11 Feb 2008 D Saldana MDS Added Kirin3 conditional text setting Applied Kirin3 conditional text 1 33 12 Feb 2008 D Saldana MDS Kirin3 Rev 0 Draft A 1 34 22 Feb 2008 E Southers EDS...

Page 568: ...Pulse Width Modulation PWM Module MCF52277 Reference Manual Rev 1 24 26 Freescale Semiconductor...

Page 569: ...odule as shown in Figure 25 1 consists of separate transmit and receive circuits with FIFO registers and separate serial clock and frame sync generation for the transmit and receive sections The secon...

Page 570: ...ipherals Audio codecs that implement the inter IC sound bus I2 S and the Intel AC97 standards Transmit Shift Reg 32 SSI_RCR TXFIFO0 8x24 TXSR Internal Bus RXFIFO0 8x24 Receive Shift Reg SSI_RX0 RXSR S...

Page 571: ...bits which can be used in network mode to provide two independent channels for transmission and reception Programmable data interface modes such as I2 S lsb msb aligned Programmable word length 8 10 1...

Page 572: ...an external codec Both modes use the concept of a frame The beginning of the frame is marked with a frame sync when programmed with continuous clock The SSI_CCR DC bits determine length of the frame d...

Page 573: ...l Frame Sync The input or output frame sync is used by the transmitter and receiver to synchronize the transfer of data The frame sync signal can be one bit or one word in length and can occur one bit...

Page 574: ...sync signal The shift direction can be defined as msb first or lsb first and there are other options on the clock and frame sync Figure 25 3 Serial Clock and Frame Sync Timing SSI Internal Continuous...

Page 575: ...0 0xFC0B_C00C SSI Receive Data Register 1 SSI_RX1 32 R 0x0000_0000 25 3 4 25 10 0xFC0B_C010 SSI Control Register SSI_CR 32 R W 0x0000_0000 25 3 7 25 12 0xFC0B_C014 SSI Interrupt Status Register SSI_IS...

Page 576: ...most significant portion of the shift register if SSI_TCR TXBIT0 is cleared Otherwise it occupies the least significant portion The unused portion of the register is ignored Address 0xFC0B_C000 SSI_T...

Page 577: ...st If this bit is set the least significant bit lsb is shifted out first The following figures show the transmitter loading and shifting operation They illustrate some possible values for WL which can...

Page 578: ...21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SSI_RX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25 9 SSI Receive Data Registers SSI_RX0 SSI_RX1 Table 2...

Page 579: ...d in by the bit clock when the associated frame sync is asserted When a gated clock is used data is shifted in by the gated clock Data is assumed to be received msb first if SSI_RCR SHFD is cleared If...

Page 580: ...Control Register SSI_CR The SSI control register sets up the SSI modules SSI operating modes are selected in this register except AC97 mode which is selected in SSI_ACR register SSI_RX 31 0 SSI_RXD 3...

Page 581: ...ely and while transmitting data is alternately transferred from SSI_TX0 and SSI_TX1 to TXSR Two channel operation can be enabled for an even number of slots larger than two to optimize usage of both F...

Page 582: ...ption 0 Receiver disabled 1 Receiver enabled 1 TE Transmitter Enables the transfer of the contents of the SSI_TX registers to the TXSR and also enables the internal transmit clock The transmit section...

Page 583: ...difference in the previous and current value of the received command address This bit is cleared upon reading the SSI_ACADD register 0 No change in SSI_ACADD register 1 SSI_ACADD register updated wit...

Page 584: ...data 1 interrupt Required conditions Trigger Enabled SSI_IER RIE set SSI_IER RFF1 set SSI_ISR RFF1 sets Disabled SSI_IER RIE set SSI_IER RDR1 set SSI_RX1 loaded with new value Rx FIFO1 RDR1 is set wh...

Page 585: ...ror 1 Only valid in two channel mode When a transmit underrun error occurs the previous data is retransmitted In network mode each time slot requires data transmission unless masked through the SSI_TM...

Page 586: ...eive frame sync Indicates occurrence of a receive frame sync during reception of the next word in SSI_RX registers Table 25 8 SSI_ISR Field Descriptions continued Field Description SSI Mode Transmit f...

Page 587: ...Receive FIFO 0 is full Table 25 8 SSI_ISR Field Descriptions continued Field Description Last time slot interrupts Required conditions Trigger TLS SSI_IER TIE set SSI_IER TLS set SSI_ISR TLS sets RLS...

Page 588: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 RDMAE RIE TDMAE TIE CMD AU CMDU RXT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RDR1 RDR0 TDE1 TD...

Page 589: ...nable If the Tx FIFO is enabled a DMA request generates when either of the SSI_ISR TFE0 1 bits is set If the Tx FIFO is disabled a DMA request generates when either of the SSI_ISR TDE0 1 bits is set 0...

Page 590: ...IR Clock direction Controls the direction and source of the clock signal on the SSI_BCLK pin Refer to Table 25 3 for details of clock port configuration 0 Clock is external 1 Clock generated internall...

Page 591: ...ceive bit 0 Alignment Allows SSI to receive the data word at bit position 0 or 15 31 in the receive shift register The shifting data direction can be msb or lsb first controlled by the RSHFD bit 0 msb...

Page 592: ...ng 1 Receive frame sync is one bit clock period long 0 REFS Receive early frame sync Controls when the frame sync is initiated for the receive section The frame sync is disabled after one bit for bit...

Page 593: ...al mode a divide ratio of 1 DC 00000 provides continuous periodic data word transfer A bit length frame sync must be used in this case otherwise in word length mode the frame sync is always asserted 7...

Page 594: ...uals 0x8 Else Reserved 19 16 TFWM1 Transmit FIFO empty watermark 1 Controls the threshold at which the SSI_ISR TFE1 flag is set The TFE1 flag is set when the data level in Tx FIFO 1 falls below the se...

Page 595: ...FRDIV WR RD TIF FV AC97EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25 21 SSI AC97 Control Register SSI_ACR Table 25 15 SSI_ACR Field Descriptions Field Descripti...

Page 596: ...0 1 FV Fixed variable operation 0 AC97 fixed mode 1 AC97 variable mode 0 AC97EN AC97 mode enable Refer to Section 25 4 1 5 AC97 Mode for details of AC97 operation 0 AC97 mode disabled 1 AC97 mode enab...

Page 597: ...received in the incoming command data slot can update these bits If the contents of these bits change due to an update the SSI_ISR CMDDU bit is set During an AC97 read command 0x0_0000 in time slot 2...

Page 598: ...n the current frame Each bit corresponds to the respective time slot in the frame If a change is made to the register contents the transmission pattern is updated from the next time slot Transmit mask...

Page 599: ...used 3 Write data to transmit data register SSI_TX0 4 Transmitter enabled TE 1 5 Frame sync active for continuous clock case 6 Bit clock begins for gated clock case When the above conditions occur in...

Page 600: ...to the receive FIFO 0 Figure 25 27 shows transmitter and receiver timing for an 8 bit word with two words per time slot in normal mode and continuous clock with a late word length frame sync The Tx da...

Page 601: ...frame In this mode the frame is divided into more than one time slot During each time slot one data word can be transferred rather than in the frame sync time slot as in normal mode Each time slot is...

Page 602: ...ubsequent data is sent to FIFO 1 and FIFO 0 alternately Time slots are selected through the transmit and receive time slot mask registers SSI_TMASK and SSI_RMASK 25 4 1 2 1 Network Mode Transmit The t...

Page 603: ...ich sets the RDR bit This causes a receive interrupt to occur if the the RIE bit is set The second data word second time slot in the frame begins shifting in immediately after the transfer of the firs...

Page 604: ...RX register at the end of each time slot If the FIFO is disabled RDR flag sets and causes a receiver interrupt if the RE RIE and SSI_IER RDR bits are set If the FIFO is enabled the RFF flag generates...

Page 605: ...peripheral devices In gated clock mode presence of the clock indicates that valid data is on the SSI_TXD or SSI_RXD signals For this reason no frame sync is needed in this mode After transmission of...

Page 606: ...ifted in Care should be taken to clear all DC bits when the module is used in gated mode For gated clock operated in external clock mode proper clock signalling must apply to SSI_BCLK for it to functi...

Page 607: ...1 4 I2 S Mode The SSI is compliant to I2 S bus specification from Philips Semiconductors February 1986 Revised June 5 1996 Figure 25 35 depicts basic I2 S protocol timing Figure 25 35 I2 S Mode Timin...

Page 608: ...The processor automatically performs these settings when in I2 S master mode Network mode is selected SSI_CR NET 1 Tx frame sync length set to one word long frame SSI_TCR TFSL 0 Rx frame sync length...

Page 609: ...the start of a frame and the rest of the slots in that frame are all 20 bits wide The same sequence is followed while receiving data Refer to the AC97 specification for details regarding transmit and...

Page 610: ...and address and command data slots slots 1 and 2 are always 20 bits wide 2 Select the number of time slots through the SSI_CCR DC bits For AC97 operation the DC bits should be set to a value of 0xC re...

Page 611: ...sources Having this choice allows the user to operate the SSI module at frequencies that would not be achievable if standard internal core clock frequencies are used This is also the output master cl...

Page 612: ...scaler for bit rate clock generation A programmable frame rate divider and a word length divider are used for frame rate sync signal generation Figure 25 37 shows a block diagram of the clock generato...

Page 613: ...n be 64 2 8 4 kHz In the next example SSI_CLOCK is 12 MHz A 16 bit word network mode with DC 1 PM 1 the PSR 0 DIV2 1 a bit clock rate of 12 14 2 1 5MHz is generated Because the 16 bit word rate equals...

Page 614: ...ition of SSI_FS should be synchronized with the rising edge of external clock signal SSI_BCLK 25 4 4 Supported Data Alignment Formats The SSI supports three data formats to provide flexibility with ma...

Page 615: ...st significant bit This format is useful when data is stored in a fixed point integer format which implies fractional values Table 25 24 Data Alignment Format Bit Number 31 30 29 28 27 26 25 24 23 22...

Page 616: ...e the receive data register full condition Reading the SSI_RX registers clears the RDR bits thus clearing the pending interrupt Two receive data interrupts two per channel in two channel mode are avai...

Page 617: ...ed by the power on reset The SSI control bits including those in SSI_CR are unaffected The SSI reset is useful for selective reset of the SSI without changing the present SSI control bits and without...

Page 618: ...Requiring SSI to be Disabled Before Change Control Register Bit SSI_CR 9 CIS 8 TCH 7 MCE 6 5 I2S 4 SYN 3 NET SSI_IER 22 RDMAE 20 TDMAE SSI_RCR SSI_TCR 9 RXBIT0 TXBIT0 8 RFEN1 TFEN1 7 RFEN0 TFEN0 6 TF...

Page 619: ...lock Block Diagram 26 1 1 Overview This section discusses how to operate and program the real time clock RTC module that maintains a time of day clock provides stopwatch alarm and interrupt functions...

Page 620: ...are located in three registers RTC_SECONDS contains the 6 bit seconds counter RTC_HOURMIN contains the 6 bit minutes counter and 5 bit hours counter RTC_DAYS contains the 16 bit day counter Alarm Ther...

Page 621: ...emory Map Address Register Width bits Access Reset Value Section Page 0xFC03_C000 RTC Hours and Minutes Counter Register RTC_HOURMIN 32 R W Undefined 26 3 1 26 3 0xFC03_C004 RTC Seconds Counter Regist...

Page 622: ...3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOURS 0 0 MINUTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 2 RTC Hours and Minutes Counter Register RTC_HOURMIN Table 26 3 RTC_HOURM...

Page 623: ...0 0 MINUTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 4 RTC Hours and Minutes Alarm Register RTC_ALRM_HM Table 26 5 RTC_ALRM_HM Field Descriptions Field Descri...

Page 624: ...0 0 SWR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Figure 26 6 RTC Control Register RTC_CR Table 26 7 RTC_CR Field Descriptions Field Description 31 8 Reserved must be cle...

Page 625: ...our interrupt flag If enabled this bit is set on every increment of the hour counter in the RTC_HOURMIN register 0 No interrupt has occurred 1 An hour interrupt has occurred 4 1HZ 1 Hz interrupt flag...

Page 626: ...M7 0 interrupt disabled 1 SAM7 0 interrupt enabled 7 2HZ 2 Hz interrupt enable 0 Interrupt disabled 1 2 Hz interrupt enabled 6 Reserved must be cleared 5 HR Hour interrupt enable 0 Interrupt disabled...

Page 627: ...25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Fi...

Page 628: ...te 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAYS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 629: ...d in three registers The 6 bit seconds counter is located in RTC_SECONDS The 6 bit minutes counter and the 5 bit hours counter are located in RTC_HOURMIN The 16 bit day counter is located in RTC_DAYS...

Page 630: ...ing timer operates only if the real time clock is enabled and the 1 Hz signal is programmed to clock at 1 Hz The sample clock which is equal to SAM7 generates by dividing the RTC oscillator frequency...

Page 631: ...ange until it is reprogrammed The actual delay includes the seconds from setting the stopwatch to the next minute tick 26 5 Initialization Application Information 26 5 1 Flow Chart of RTC Operation Ta...

Page 632: ...or Figure 26 15 Flow Chart of Alarm and Time of Day Programming Clear any incidental alarm interrupt Enable the alarm interrupt Disable the alarm interrupt Program the alarm or time of day registers c...

Page 633: ...ulus register or it can be a free running down counter 27 1 2 Block Diagram Figure 27 1 PIT Block Diagram 27 1 3 Low Power Mode Operation This subsection describes the operation of the PIT modules in...

Page 634: ...exited the PIT continues to operate in its pre debug mode state but any updates made in debug mode remain 27 2 Memory Map Register Definition This section contains a memory map see Table 27 2 and des...

Page 635: ...t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27 2 PCSRn Register Table 27 3 PCSRn Field Descriptions Field Description 15 12 Reserved must be cleared 11 8 PRE Prescaler The read write prescaler bits selec...

Page 636: ...ug mode but any updates made in debug mode remain 0 PIT function not affected in debug mode 1 PIT function stopped in debug mode Note Changing the DBG bit from 1 to 0 during debug mode starts the PIT...

Page 637: ...interrupt request to the CPU Address 0xFC08_0002 PMR0 0xFC08_4002 PMR1 Access Supervisor read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PM W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 27 3 PIT M...

Page 638: ...Rn PIF flag is set If the PCSRn PIE bit is set PIF flag issues an interrupt request to the CPU When the PCSRn OVW bit is set counter can be directly initialized by writing to PMRn without having to wa...

Page 639: ...e Semiconductor 27 7 The PIF flag is set when the PIT counter reaches 0x0000 The PIE bit enables the PIF flag to generate interrupt requests Clear PIF by writing a 1 to it or by writing to the PMR Tab...

Page 640: ...Programmable Interrupt Timers PIT0 PIT1 MCF52277 Reference Manual Rev 1 27 8 Freescale Semiconductor...

Page 641: ...1 DTIM2 or DTIM3 28 1 1 Overview Each DMA timer module has a separate register set for configuration and control The timers can be configured to operate from the internal bus clock or from an external...

Page 642: ...quest on input capture or reference compare Ability to stop the timer from counting when the ColdFire core is halted 28 2 Memory Map Register Definition The timer module registers shown in Table 28 1...

Page 643: ...Register DTXMRn 8 R W 0x00 28 2 2 28 4 0xFC07_0003 0xFC07_4003 0xFC07_8003 0xFC07_C003 DMA Timer n Event Register DTERn 8 R W 0x00 28 2 3 28 5 0xFC07_0004 0xFC07_4004 0xFC07_8004 0xFC07_C004 DMA Timer...

Page 644: ...d does not affect DMA request or interrupt on capture function 1 Enable DMA request or interrupt upon reaching the reference value 3 FRR Free run restart 0 Free run Timer count continues incrementing...

Page 645: ...EN DMA request Enables DMA request output on counter reference match or capture edge event 0 DMA request disabled 1 DMA request enabled 6 HALTED Controls the counter when the core is halted This allow...

Page 646: ...The counter value DTCNn equals the reference value DTRRn Writing a 1 to REF clears the event condition Writing a 0 has no effect 0 CAP Capture event The counter value has been latched into DTCRn Writi...

Page 647: ...xFC07_0004 DTRR0 0xFC07_4004 DTRR1 0xFC07_8004 DTRR2 0xFC07_C004 DTRR3 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R REF 32 bit referen...

Page 648: ...quest is asserted If DTERn CAP is set and DTXMRn DMAEN is cleared an interrupt is asserted 28 3 3 Reference Compare Each DMA timer can be configured to count up to a reference value at which point DTE...

Page 649: ...he timer capture mode is selected or indeterminate operation results The 8 bit DTMRn PS prescaler value is set Using DTMRn RST counter is cleared and started Timer events are managed with an interrupt...

Page 650: ...RST T0_LOOP move b TER0 D1 load TER0 and see if btst 1 D1 TER0 REF has been set beq T0_LOOP addi l 1 D2 Increment D2 cmp l 5 D2 Did D2 reach 5 i e timer ref has timed beq T0_FINISH If so end timer0 e...

Page 651: ...e DSPI Figure 29 1 DSPI Block Diagram 29 1 2 Overview The DMA serial peripheral interface DSPI block provides a synchronous serial bus for communication between an MCU and an external peripheral devic...

Page 652: ...mode for low latency updates to SPI queues Programmable transfer attributes on a per frame basis Eight clock and transfer attribute registers Serial clock with programmable polarity and phase Program...

Page 653: ...re controlled by the SPI command in the current TX FIFO entry The CTAS field in the SPI command selects which of the eight DSPI_CTARs sets the transfer attributes Transfer attribute control is on a fr...

Page 654: ...l chip select output that selects the slave device to which the current transmission is intended In slave mode the DSPI_SS signal is a slave select input signal allowing an SPI master to select the DS...

Page 655: ...t at reset Table 29 2 DSPI Module Memory Map Address Register Width Access Reset Value Section Page 0xFC05_C000 Module Configuration Register DSPI_MCR 32 R W 0x0000_4001 29 3 1 29 5 0xFC05_C008 DSPI T...

Page 656: ...tion may occur 0 Slave mode 1 Master mode 30 CONT_ SCKE Continuous SCK enable Enables the serial communication clock DSPI_SCK to run continuously See Section 29 4 5 Continuous Serial Communications Cl...

Page 657: ...eatures for more information This bit is set at reset 0 Enable DSPI clocks 1 Allow external logic to disable DSPI clocks 13 DIS_TX Disable transmit FIFO When the TX FIFO is disabled transmit part of t...

Page 658: ...nd polarity data bit ordering baud rate and various delays When DSPI is configured as an SPI master the DSPI_PUSHR CTAS field in the command portion of the TX FIFO entry selects which of the DSPI_CTAR...

Page 659: ...munications clock SCK This field is only used in master mode It effectively halves the baud rate division ratio supporting faster frequencies and odd division ratios for the serial communications cloc...

Page 660: ...ngs Note When the continuous selection format is selected CONT or DCONT is set switching between clock phases without stopping the DSPI can cause errors in the transfer 0 Data is captured on the leadi...

Page 661: ...I_PCS prescaler 11 7 clock delay between negation of DSPI_PCS to assertion of next DSPI_PCS prescaler 17 16 PBR Baud rate prescaler Selects the prescaler value for the baud rate This field is only use...

Page 662: ...transfer is the time between the negation of the DSPI_PCS signal at the end of a frame and the assertion of DSPI_PCS at the beginning of the next frame The table below lists the scaler values Note See...

Page 663: ...frequency of the DSPI_SCK The table below lists the baud rate scaler values Note See Section 29 4 3 1 Baud Rate Generator for more details on calculating the baud rate Address 0xFC05_C02C DSPI_SR Acc...

Page 664: ...FO has occurred The transmit underflow condition is detected only for DSPI modules operating in slave mode The TFUF bit is set when the TX FIFO of a DSPI operating in slave mode is empty and a transfe...

Page 665: ...CTR RX FIFO counter Indicates the number of entries in the RX FIFO The RXCTR is decremented every time the DSPI_POPR is read The RXCTR is incremented after the last incoming databit is sampled but bef...

Page 666: ...s are enabled 24 TFFF_DIRS Transmit FIFO fill DMA or interrupt request select Selects between generating a DMA request or an interrupt request When the DSPI_SR TFFF flag bit and the DSPI_RSER TFFF_RE...

Page 667: ...en transfers 30 28 CTAS Clock and transfer attributes select Selects which of the DSPI_CTARn registers is used to set the transfer attributes for the associated SPI frame This field is used only in SP...

Page 668: ...ch DSPI_PCSn signals are asserted for the transfer This bit is used only in SPI master mode 0 Negate the DSPI_PCSn signal 1 Assert the DSPI_PCSn signal Note DSPI_PCS7 DSPI_PCS6 DSPI_PCS5 DSPI_PCS4 and...

Page 669: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TXCMD TXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29 9 DSPI_TXFRn Register 0 15 Table 29 10 DSPI_TXFRn Field Descriptions...

Page 670: ...shift register is now in the shift register of the slave and vice versa At the end of a transfer the DSPI_SR TCF bit is set to indicate a completed transfer Figure 29 11 illustrates how master and sla...

Page 671: ...a first in first out FIFO buffer The received data is stored in entries in the receive FIFO RX FIFO buffer Host software or the eDMA controller transfers the received data from the RX FIFO to memory e...

Page 672: ...set in the DSPI_CTAR0 register 29 4 2 3 FIFO Disable Operation The FIFO disable mechanisms allow SPI transfers without using the TX or RX FIFOs The DSPI operates as a double buffered simplified SPI wh...

Page 673: ...Draining the TX FIFO The TX FIFO entries are removed drained by shifting SPI data out through the shift register Entries are transferred from the TX FIFO to the shift register and shifted out as long...

Page 674: ...3 7 DSPI POP RX FIFO Register DSPI_POPR A read of the DSPI_POPR decrements the RX FIFO counter by one Attempts to pop data from an empty RX FIFO are ignored and the RX FIFO counter remains unchanged...

Page 675: ...e after SCK delay The relationship between these variables is given in the following Eqn 29 3 Table 29 15 shows an example of the computed after SCK delay 29 4 3 4 Delay after Transfer tDT The delay a...

Page 676: ...ifferent transfer formats Classic SPI with CPHA 0 Classic SPI with CPHA 1 Modified transfer format with CPHA 0 Modified transfer format with CPHA 1 A modified transfer format is supported to allow for...

Page 677: ...n CPHA is cleared At the next to last serial clock edge of the frame edge 15 of Figure 29 14 Master s TCF and EOQF are set and RXCTR counter is updated At the last serial clock edge of the frame edge...

Page 678: ...master If DSPI_CTARn CPHA is set At the last serial clock edge edge 16 of Figure 29 15 Master s EOQF and TCF are set Slave s TCF is set Master s and slave s RXCTR counters are updated 29 4 4 3 Modifi...

Page 679: ...ts the point where the master samples the slave DSPI_SOUT Table 29 17 lists the number of system clock cycles between the active edge of DSPI_SCK and the master sample point for different values of th...

Page 680: ...during the sampling of the last bit The SCK to PCS delay must be greater or equal to half of the DSPI_SCK period NOTE For correct operation of the modified transfer format the user must thoroughly an...

Page 681: ...ot include a half clock period The default settings for these provide a total of four system clocks In many situations tASC and tCSC must be increased if a full half clock period is required Switching...

Page 682: ...is set Clearing CPHA is ignored if the CONT_SCKE bit is set Continuous SCK is supported for modified transfer format Clock and transfer attributes for the continuous SCK mode are set according to the...

Page 683: ...nterrupts DMA Requests The DSPI has six conditions that can only generate interrupt requests and two conditions that can generate an interrupt or DMA request Table 29 18 lists these conditions Table 2...

Page 684: ...umber of possible entries and the DSPI_RSER TFFF_RE bit is set The DSPI_RSER TFFF_DIRS bit selects whether a DMA request or an interrupt request is generated 29 4 6 3 Transfer Complete Interrupt Reque...

Page 685: ...FO underflow signals 29 4 7 Power Saving Features The DSPI supports two power saving strategies Module disable mode clock gating of non memory mapped logic Clock gating of slave interface signals and...

Page 686: ...red to memory receive queue by reading the DSPI_SR RXCNT bit or by checking the DSPI_SR RFDF bit after each read operation of the DSPI_POPR register 7 Modify DMA descriptor of TX and RX channels for n...

Page 687: ...er Values DSPI_CTARn PBR 2 3 5 7 Baud Rate Scaler Values DSPI_CTARn BR 2 25 0MHz 16 7MHz 10 0MHz 7 14MHz 4 12 5MHz 8 33MHz 5 00MHz 3 57MHz 6 8 33MHz 5 56MHz 3 33MHz 2 38MHz 8 6 25MHz 4 17MHz 2 50MHz 1...

Page 688: ...FIFO is chosen for the illustration but the concepts carry over to the RX FIFO See Section 29 4 2 4 TX FIFO Buffering Mechanism and Section 29 4 2 5 RX FIFO Buffering Mechanism for details on the FIF...

Page 689: ...se address of TX FIFO TXCTR TX FIFO counter TXNXTPTR transmit next pointer TX FIFO depth 16 29 5 5 2 Address Calculation for the First in and Last in Entries in the RX FIFO The memory address of the f...

Page 690: ...DMA Serial Peripheral Interface DSPI MCF52277 Reference Manual Rev 1 29 40 Freescale Semiconductor...

Page 691: ...ndent UARTs eliminating the need for an external UART clock As Figure 30 1 shows each UART module interfaces directly to the CPU and consists of Serial communication channel Programmable clock generat...

Page 692: ...interrupt driven or use DMA requests for servicing See Section 30 4 2 2 Receiver NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins refer to Chapter 14...

Page 693: ...TE Interrupt can mean an interrupt request asserted to the CPU or a DMA request Table 30 1 UART Module Signals Signal Description UnTXD Transmitter Serial Data Output UnTXD is held high mark condition...

Page 694: ...s UTBn 8 W 0x00 30 3 7 30 12 0xFC06_0010 0xFC06_4010 0xFC06_8010 UART Input Port Change Register UIPCRn 8 R See Section 30 3 8 30 12 UART Auxiliary Control Register UACRn 8 W 0x00 30 3 9 30 13 0xFC06_...

Page 695: ...ontrol is disabled for both Transmitter RTS control is configured in UMR2n TXRTS 0 The receiver has no effect on UnRTS 1 When a valid start bit is received UnRTS is negated if the UART s FIFO is full...

Page 696: ...racter Selects the number of data bits per character to be sent The values shown do not include start parity or stop bits 00 5 bits 01 6 bits 10 7 bits 11 8 bits Address 0xFC06_0000 UMR20 0xFC06_4000...

Page 697: ...ontrols the operation of the transmitter 0 UnCTS has no effect on the transmitter 1 Enables clear to send operation The transmitter checks the state of UnCTS each time it is ready to send a character...

Page 698: ...esponding character in the FIFO was received with incorrect parity If UMR1n PM equals 11 multidrop PE stores the received address or data A D bit PE is valid only when RXRDY is set 4 OE Overrun error...

Page 699: ...ed and the receiver FIFO is now full Any characters received when the FIFO is full are lost 0 RXRDY Receiver ready 0 The CPU has read the receive buffer and no characters remain in the FIFO after this...

Page 700: ...command instead of RECEIVER DISABLE when reconfiguring the receiver 011 RESET TRANSMITTER Immediately disables the transmitter and clears USRn TXEMP TXRDY No other registers are altered Because it pl...

Page 701: ...nsmitter is already enabled this command has no effect 10 TRANSMITTER DISABLE Terminates transmitter operation and clears USRn TXEMP TXRDY If a character is being sent when the transmitter is disabled...

Page 702: ...hen the UART s TXRDY is cleared and the transmitter is disabled have no effect on the transmit buffer Figure 30 9 shows UTBn TB contains the character in the transmit buffer 30 3 8 UART Input Port Cha...

Page 703: ...Reading UIPCRn clears UISRn COS 1 A change of state longer than 25 50 s occurred on the UnCTS input UACRn can be programmed to generate an interrupt to the CPU when a change of state is detected 3 1...

Page 704: ...0 No new break change condition to report Section 30 3 5 UART Command Registers UCRn describes the RESET BREAK CHANGE INTERRUPT command 1 The receiver detected the beginning or end of a received break...

Page 705: ...eceiver are enabled UBG1n and UBG2n are write only and cannot be read by the CPU 30 3 12 UART Input Port Register UIPn The UIPn registers shown in Figure 30 15 show the current state of the UnCTS inpu...

Page 706: ...aud rates Table 30 11 UIPn Field Descriptions Field Description 7 1 Reserved 0 CTS Current state of clear to send The UnCTS value is latched and reflects the state of the input pin when UIPn is read N...

Page 707: ...or internal bus clock is programmed in the UCSR Figure 30 17 Clocking Source Diagram NOTE If DTnIN is a clocking source for the timer or UART that timer module cannot use DTnIN for timer input captur...

Page 708: ...y Map Register Definition Figure 30 18 Transmitter and Receiver Functional Diagram 30 4 2 1 Transmitter The transmitter is enabled through the UART command register UCRn When it is ready to accept a c...

Page 709: ...reenabled through the UCRn to resume operation after a disable or software reset If the clear to send operation is enabled UnCTS must be asserted for the character to be transmitted If UnCTS is negate...

Page 710: ...er number of data bits and parity if any is assembled and one stop bit is detected Data on the UnRXD input is sampled on the rising edge of the programmed clock source The lsb is received first The da...

Page 711: ...ces an all zero character into the Rx FIFO and sets USRn RB RXRDY Figure 30 20 shows receiver functional timing Figure 30 20 Receiver Timing Diagram 30 4 2 3 FIFO The FIFO is used in the UART s receiv...

Page 712: ...only when the receive buffer is read The USRn should be read before reading the receive buffer If all three receiver holding registers are full a new character is held in the receiver shift register u...

Page 713: ...by sending data to the transmitter and checking data assembled by the receiver to ensure proper operations Figure 30 22 Local Loopback Features of this local loopback mode are Transmitter and CPU to r...

Page 714: ...dress character the slave receiver notifies its respective CPU by setting USRn RXRDY and generating an interrupt if programmed to do so Each slave station CPU then compares the received address to its...

Page 715: ...ed A D bit is 0 data tag If the receiver is enabled all received characters are transferred to the CPU through the receiver holding register during read operations In either case data bits load into t...

Page 716: ...e UART in local loopback mode and checks for the following errors Transmitter never ready Receiver never ready Parity error Incorrect character received I O driver routine This routine See Sheet 4 p 3...

Page 717: ...ssion status Similarly the receive DMA request signal is asserted when the FIFO full or receive ready FFULL RXRDY flag in the interrupt status register UISRn FFULL RXRDY is set When the receive DMA re...

Page 718: ...UMR1n a If preferred program operation of receiver ready to send RXRTS bit a Select receiver ready or FIFO full notification RXRDY FFULL bit b Select character or block error mode ERR bit c Select par...

Page 719: ...reescale Semiconductor 30 29 Figure 30 25 UART Mode Programming Flowchart Sheet 1 of 5 Serial Module SINIT Initiate Channel Interrupts CHK1 Call CHCHK Save Channel Status Enable Any Errors Y N Enable...

Page 720: ...art Sheet 2 of 5 CHCHK CHCHK Place Channel In Local Loopback Mode Enable Transmitter Clear Status Word TxCHK Is Transmitter Ready Y N SNDCHR RxCHK Send Character To Transmitter Has Character Been Rece...

Page 721: ...Programming Flowchart Sheet 3 of 5 A B B FRCHK Have Framing Error Set Framing Error Flag PRCHK Have Parity Error Set Parity Error Flag Get Character From Receiver Same As Transmitted Character Set Inc...

Page 722: ...y Beginning Of A Break SIRQ ABRKI N Clear Change in Break Status Bit ABRKI1 N Has End of break IRQ Arrived Yet Y Y Clear Change in Break Status Bit Remove Break Character From Receiver FIFO Replace Re...

Page 723: ...UART Modules MCF52277 Reference Manual Rev 1 Freescale Semiconductor 30 33 Figure 30 25 UART Mode Programming Flowchart Sheet 5 of 5 OUTCH Is Transmitter Ready N Y Send Character To Transmitter Return...

Page 724: ...UART Modules MCF52277 Reference Manual Rev 1 30 34 Freescale Semiconductor...

Page 725: ...am of the I2 C module Figure 31 1 I2C Module Block Diagram Figure 31 1 shows the I2 C registers described in Section 31 2 Memory Map Register Definition Address Compare In Out Data Shift Start Stop In...

Page 726: ...a true multiple master bus it uses arbitration and collision detection to prevent data corruption in the event that multiple devices attempt to control the bus simultaneously This feature supports co...

Page 727: ...a programmable prescaler to configure the I2C clock for bit rate selection Table 31 1 I2C Module Memory Map Address Register Access Reset Value Section Page 0xFC05_8000 I2 C Address Register I2ADR R...

Page 728: ...clock divided by the divider shown below Due to potentially slow I2C_SCL and I2C_SDA rise and fall times bus signals are sampled at the prescaler frequency IC Divider IC Divider IC Divider IC Divider...

Page 729: ...rrupts are enabled An I2C interrupt occurs if I2SR IIF is also set 5 MSTA Master slave mode select bit If the master loses arbitration MSTA is cleared without generating a STOP signal 0 Slave mode Cha...

Page 730: ...er drives high during an address or data transmit cycle I2C_SDA sampled low when the master drives high during the acknowledge bit of a data receive cycle A start cycle is attempted when the bus is bu...

Page 731: ...ignal see A in Figure 31 7 A START signal is defined as a high to low transition of I2C_SDA while I2C_SCL is high This signal denotes the beginning of a data transfer each data transfer can be several...

Page 732: ...tion specified by the R W bit sent by the calling master Data can be changed only while I2C_SCL is low and must be held stable while I2C_SCL is high as Figure 31 7 shows I2C_SCL is pulsed once for eac...

Page 733: ...I2C_SDA for the master to generate a STOP or START signal Figure 31 9 31 3 5 STOP Signal The master can terminate communication by generating a STOP signal to free the bus A STOP signal is defined as...

Page 734: ...ve in a different mode without releasing the bus The master transmits data to the slave first and then the master reads data from slave by reversing the R W bit Figure 31 11 Data Transfer Combined For...

Page 735: ...ow periods enter a high wait state during this time see Figure 31 12 When all devices concerned have counted off their low period the synchronized clock I2C_SCL line is released and pulled high At thi...

Page 736: ...See Section 31 2 2 I2C Frequency Divider Register I2FDR 2 Update the I2ADR to define its slave address 3 Set I2CR IEN to enable the I2 C bus interface system 4 Modify the I2CR to select or deselect ma...

Page 737: ...the IIF bit if the interrupt function is disabled Polling should monitor IIF rather than ICF because that operation is different when arbitration is lost When an interrupt occurs at the end of the ad...

Page 738: ...IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred interrupts resulting from subsequent data transfers have IAAS cleared A data transfer can now...

Page 739: ...y Read from I2DR Generate STOP Signal Read Data from I2DR And Store Set TXAK 1 Generate STOP Signal 2nd Last Byte to be Last Byte to be Arbitration Lost Clear IAL IAAS 1 IAAS 1 SRW 1 Tx Rx Set TX Mode...

Page 740: ...I2 C Interface MCF52277 Reference Manual Rev 1 31 16 Freescale Semiconductor...

Page 741: ...cessor complex is halted and a variety of commands can be sent to the processor to access memory registers and peripherals The external emulator uses a three pin serial full duplex channel See Section...

Page 742: ...e breakpoint logic Added BDM address attribute register BAAR BKPT configurable interrupt CSR BKD Level 1 and level 2 triggers on OR condition in addition to AND SYNC_PC command to display the processo...

Page 743: ...ATA port The core stalls until one FIFO entry is available Processor Status Clock PSTCLK Delayed version of the processor clock Its rising edge appears in the center of valid PST and DDATA output PSTC...

Page 744: ...NC_PC command issued For some opcodes a branch target address may be displayed on DDATA depending on the CSR settings CSR also controls the number of address bytes displayed indicated by the PST marke...

Page 745: ...target address displayed on this port is configurable 2 3 or 4 bytes where the encoding is 0x9 0xA and 0xB respectively Another example of a variant branch instruction would be a JMP A0 instruction F...

Page 746: ...PU through the WDEBUG instruction These control registers are write only from the programming model and they can be written through the BDM port using the WDMREG command In addition the configuration...

Page 747: ...ry commands and has the same format as the LSB of the AATR The registers containing the BDM memory address and the BDM data are not program visible 32 4 2 Configuration Status Register CSR The CSR def...

Page 748: ...n emulator could use this information to identify the level of functionality supported 0000 Revision A 0001 Revision B 0010 Revision C 0011 Revision D 1001 Revision B This is the value used for this d...

Page 749: ...cutes one instruction at a time with no overlap This adds at least 5 cycles to the execution time of each instruction Given an average execution latency of 1 6 cycles instruction throughput in non pip...

Page 750: ...output core output signal is asserted 0 DBGH Disable debug signal assertion during core halt The debug mode output to the on chip peripherals is logically defined as Debug mode output CSR FDBG CSR DBG...

Page 751: ...write only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W RM SZM TTM TMM R SZ TT TM Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Figure 32 5 Address Attribute Trigger Register AATR Table 32 8 AATR Field Descript...

Page 752: ...register 0x07 using the WDEBUG instruction and through the BDM port using the WDMREG command 4 3 TT Transfer Type Compared with the local bus transfer type signals 00 Normal processor access 01 Reser...

Page 753: ...2 Breakpoint Global enable for the breakpoint trigger 0 Disables all level 2 breakpoints 1 Enables all level 2 breakpoint triggers 28 22 L2ED Enable Level 2 Data Breakpoint Setting an L2ED bit enable...

Page 754: ...Data_condition 1 Level 2 trigger PC_condition Address_range Data_condition Note Debug Rev A only had the AND condition available for the triggers 14 L1T Level 1 Trigger Determines the logic operation...

Page 755: ...n the DBR contents 0 No inversion 1 Invert data breakpoint comparators 4 2 L1EA Enable Level 1 Address Breakpoint Setting an L1EA bit enables the corresponding address breakpoint Clearing all three bi...

Page 756: ...3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Address Reset Figure 32 7 PC Breakpoint Register PBR0 Table 32 10 PBR0 Field Descriptions Field Description 31 0 Address PC Breakpoint...

Page 757: ...24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Mask Reset Figure 32 9 PC Breakpoint Mask Register PBMR Table 32 12 PBMR Field Descriptions Field Description 31 0 Mask PC Breakpoi...

Page 758: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Data Reset Figure 32 11 Data Breakpoint Registers DBR Table 32 15 DBR Field Descriptions Field Description 31 0 Dat...

Page 759: ...g Provides absolute control of the processor and thus the system This feature allows quick hardware debugging with the same tool set used for firmware development 32 5 1 CPU Halt Although most BDM ope...

Page 760: ...lly if the PC register was loaded the GO command causes the processor to exit halted state and pass control to the instruction address in the PC bypassing normal reset exception processing If the PC w...

Page 761: ...cate the start of a serial transfer The development system must count clock cycles in a given transfer C0 C4 are described as C0 Set the state of the DSI bit C1 First synchronization cycle for DSI DSC...

Page 762: ...ed below The not ready response can be ignored unless a memory referencing cycle is in progress Otherwise the debug module can accept a new serial transfer after 32 processor clock periods 15 0 Data D...

Page 763: ...word Dump memory block DUMP Used with READ to dump large blocks of memory An initial READ executes to set up the starting address of the block and to retrieve the first result A DUMP command retrieves...

Page 764: ...data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Operation 0 R W Op Size 0 0 A D Register Extension Word s Figure 32 16 BDM Command Format Table 32 21 BDM Field Descriptions Field Description 15 10 Operatio...

Page 765: ...encoding If this occurs the development system should retransmit the command NOTE A not ready response can be ignored except during a memory referencing cycle Otherwise the debug module can accept a n...

Page 766: ...t for illegal commands not ready responses and transfers with bus errors Section 32 5 2 BDM Serial Interface describes the receive packet format Freescale reserves unassigned command opcodes for futur...

Page 767: ...ata is supplied most significant word first Result Data Command complete status is indicated by returning 0xFFFF with S cleared when the register write is complete 32 5 3 3 3 Read Memory Location READ...

Page 768: ...1 S 1 is returned if a bus error occurs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte Command 0x1 0x9 0x0 0x0 A 31 16 A 15 0 Result X X X X X X X X D 7 0 Word Command 0x1 0x9 0x4 0x0 A 31 16 A 15 0 Resul...

Page 769: ...e Hardware forces low order address bits to 0s for word and longword accesses to ensure that word addresses are word aligned and longword addresses are longword aligned Command Formats 15 14 13 12 11...

Page 770: ...arge blocks of memory An initial READ is executed to set up the starting address of the block and to retrieve the first result If an initial READ is not executed before the first DUMP an illegal comma...

Page 771: ...e to be dynamically altered Command Result Formats Command Sequence Figure 32 27 DUMP Command Sequence Operand Data None 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte Command 0x1 0xD 0x0 0x0 Result X X X...

Page 772: ...egister after the memory write Subsequent FILL commands use this address perform the write increment it by the current operand size and store the updated address in the temporary register If an initia...

Page 773: ...execution resumes Prefetching begins at the current address in the PC and at the current privilege level If any register such as the PC or SR is altered by a BDM command while the processor is halted...

Page 774: ...forces an instruction fetch at the next PC with the address being captured in the DDATA logic under control of the CSR BTB bits The specific sequence of PST and DDATA values is defined below 1 Debug s...

Page 775: ...isters are always 32 bits wide regardless of register width The second and third words of the command form a 32 bit address which the debug module uses to generate a special bus cycle to access the sp...

Page 776: ...R0 0x005 Access Control Register ACR1 0x 0 1 80 0x 0 1 87 Data Registers 0 7 0 load 1 store 0x 0 1 88 0x 0 1 8F Address Registers 0 7 0 load 1 store A7 is user stack pointer 0x800 Other Stack Pointer...

Page 777: ...ming model In particular any result rounding modes must be disabled during the read write process so the exact bit wise EMAC register contents are accessed For example a BDM read of an accumulator ACC...

Page 778: ...egister RDMREG Read the selected debug module register and return the 32 bit result The only valid register selection for the RDMREG command is CSR DRc 0x00 This read of the CSR clears CSR FOF TRG HAL...

Page 779: ...ta is written to the specified debug module register All 32 bits of the register are altered by the write DSCLK must be inactive while the debug module register writes from the CPU accesses are perfor...

Page 780: ...le provides four types of breakpoints PC with mask PC without mask operand address range and data with mask These breakpoints can be configured into one or two level triggers with the exact trigger re...

Page 781: ...ich occurs once per instruction Again the hardware forces the PC breakpoint to occur before the targeted instruction executes and is precise This is possible because the PC breakpoint is enabled when...

Page 782: ...in emulation mode when debug interrupt exception processing begins Setting CSR TRC forces the processor into emulation mode when trace exception processing begins While operating in emulation mode the...

Page 783: ...Status Debug Data Definition This section specifies the ColdFire processor and debug module s generation of the processor status PST and debug data DDATA output on an instruction basis In general the...

Page 784: ...Dy ea x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bclr b l data ea x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bclr b l Dy ea x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bitrev l...

Page 785: ...move l ea y ea x PST 0x1 PST 0xB DD source PST 0xB DD destination move w ea y ea x PST 0x1 PST 0x9 DD source PST 0x9 DD destination move w CCR Dx PST 0x1 move w Dy data CCR PST 0x1 movea l ea y Ax PS...

Page 786: ...PST 0xB DD destination suba l ea y Ax PST 0x1 PST 0xB DD source operand subi l data Dx PST 0x1 subq l data ea x PST 0x1 PST 0xB DD source PST 0xB DD destination subx l Dy Dx PST 0x1 swap w Dx PST 0x1...

Page 787: ...2 For JMP and JSR instructions the optional target instruction address is displayed only for those effective address fields defining variant addressing modes This includes the following ea x values An...

Page 788: ...essor is in the given mode move l MACSR Rx PST 0x1 move l MASK Rx PST 0x1 msac l Ry Rx ACCx PST 0x1 msac l Ry Rx ea y Rw ACCx PST 0x1 PST 0xB DD source operand msac w Ry Rx ACCx PST 0x1 msac w Ry Rx e...

Page 789: ...x 13 as shown below Figure 32 44 Recommended BDM Connector 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 Developer reserved1 GND GND RESET EVDD2 GND Freescale reserved GND IVDD...

Page 790: ...Debug Module MCF52277 Reference Manual Rev 1 32 50 Freescale Semiconductor...

Page 791: ...to all data and chip control pins from the board edge connector through the standard four pin test access port TAP and the JTAG reset pin TRST 33 1 1 Block Diagram Figure 33 1 shows the block diagram...

Page 792: ...d debug mode BDM for more information refer to Section 32 5 Background Debug Mode BDM JTAG_EN 0 33 2 External Signal Description The JTAG module has five input and one output external signals as descr...

Page 793: ...Mode Select Breakpoint TMS BKPT The TMS pin is the test mode select input that sequences the TAP state machine TMS is sampled on the rising edge of TCLK The TMS pin has an internal pull up resistor Th...

Page 794: ...shift DR controller states The DSO pin provides serial output data in BDM mode 33 3 Memory Map Register Definition The JTAG module registers are not memory mapped and are only accessible through the...

Page 795: ...gister on the rising edge of TCLK when the TAP state machine is in the update DR state The DSE bit selects the drive strength used in JTAG mode IR 4 0 0_0001 IDCODE Access User read only 31 30 29 28 2...

Page 796: ...odule The JTAG module consists of a TAP controller state machine which is responsible for generating all control signals that execute the JTAG instructions and read write data registers 33 4 2 TAP Con...

Page 797: ...IDCODE register for shift SAMPLE PRELOAD 00010 Selects boundary scan register for shifting sampling and preloading without disturbing functional operation SAMPLE 00011 Selects boundary scan register...

Page 798: ...and shifting in initialization data The update DR state and the falling edge of TCLK can then transfer this data to the update cells The data is applied to the external output pins by the EXTEST or C...

Page 799: ...t pins during circuit board testing HIGHZ turns off all output drivers including the 2 state drivers and selects the bypass register HIGHZ also asserts internal reset for the MCU system logic to force...

Page 800: ...emain in the low power stop mode Leaving the test logic reset state negates the ability to achieve low power but does not otherwise affect device functionality The TCLK input is not blocked in low pow...

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